公开(公告)号：US20250157889A1

公开(公告)日：2025-05-15

申请号：US18582326

申请日：2024-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Chih Hsin Yang ,  Mao-Nan Wang ,  Kuan-Hsun Wang ,  Yang-Hsin Shih ,  Yun-Sheng Li ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

Abstract: A method includes forming a first device die comprising forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate. The interconnect structure has a plurality of metal layers. The method further includes bonding a second device die to the first device die, and forming gap-fill regions surrounding the second device die. In a first formation process, a first TSV is formed to penetrate through the semiconductor substrate, wherein the first TSV has a first width. In a second formation process, a second TSV is formed to penetrate through the semiconductor substrate. The second TSV has a second width different from the first width.

公开(公告)号：US12243909B2

公开(公告)日：2025-03-04

申请号：US18395110

申请日：2023-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Dian-Hau Chen

IPC: H10B12/00 ,  H01L49/02

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.

公开(公告)号：US12230566B2

公开(公告)日：2025-02-18

申请号：US18511438

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L49/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L29/94

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

公开(公告)号：US12183697B2

公开(公告)日：2024-12-31

申请号：US18329128

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Yen-Ming Chen ,  Chih-Sheng Li ,  Hui-Chi Chen ,  Chih-Hung Lu ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L21/02

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.

公开(公告)号：US20240373758A1

公开(公告)日：2024-11-07

申请号：US18772445

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Kai-Wen Cheng ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.

公开(公告)号：US20240312885A1

公开(公告)日：2024-09-19

申请号：US18672485

申请日：2024-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Chun-Li Lin ,  Dian-Hau Chen

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/48 ,  H01L23/532

CPC classification number: H01L23/49811 ,  H01L21/02274 ,  H01L21/486 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53295

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.

公开(公告)号：US11996356B2

公开(公告)日：2024-05-28

申请号：US18329327

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Chun-Li Lin ,  Dian-Hau Chen

IPC: H01L23/495 ,  H01L21/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/532

CPC classification number: H01L23/49811 ,  H01L21/02274 ,  H01L21/486 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53295

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.

公开(公告)号：US11716910B2

公开(公告)日：2023-08-01

申请号：US17002098

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch slop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

公开(公告)号：US20220069199A1

公开(公告)日：2022-03-03

申请号：US17002098

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer

公开(公告)号：US11145564B2

公开(公告)日：2021-10-12

申请号：US16395435

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.