Invention Grant
- Patent Title: Heavily doped buried layer to reduce MOSFET off capacitance
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Application No.: US16293464Application Date: 2019-03-05
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Publication No.: US11145722B2Publication Date: 2021-10-12
- Inventor: Pengfei Wu , Susan L. Feindt , F. Jacob Steigerwald
- Applicant: Analog Devices, Inc.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L27/07 ; H01L21/74 ; H01L29/66 ; H01L29/78 ; H01L29/08 ; H01L29/73
Abstract:
A metal-oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region of a first conductivity type. The MOSFET additionally include a body region of a second conductivity type, where the body region underlies at least a portion of the source region and the drain region. The MOSFET further includes a buried region of the first conductivity type, where the buried region is disposed between the body region and a substrate, where the buried region is configured to reduce a capacitance between the source region and the drain region in response to an indicated voltage applied between the body region and the buried region.
Public/Granted literature
- US20200286997A1 HEAVILY DOPED BURIED LAYER TO REDUCE MOSFET OFF CAPACITANCE Public/Granted day:2020-09-10
Information query
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