公开(公告)号：US10522389B2

公开(公告)日：2019-12-31

申请号：US14923828

申请日：2015-10-27

Applicant: Analog Devices, Inc.

Inventor： James Fiorenza ,  F. Jacob Steigerwald ,  Edward F. Gleason ,  Susan L. Feindt

IPC: G03F7/00 ,  H01L21/762 ,  H01L25/065 ,  H01L25/00 ,  H01L21/67 ,  H01L23/525

Abstract: A transfer printing method provides a first wafer having a receiving surface, and removes a second die from a second wafer using a die moving member. Next, the method positions the second die on the receiving surface of the first wafer. Specifically, to position the second die on the receiving surface, the first wafer has alignment structure for at least in part controlling movement of the die moving member.

公开(公告)号：US11145722B2

公开(公告)日：2021-10-12

申请号：US16293464

申请日：2019-03-05

Applicant: Analog Devices, Inc.

Inventor： Pengfei Wu ,  Susan L. Feindt ,  F. Jacob Steigerwald

IPC: H01L29/10 ,  H01L27/07 ,  H01L21/74 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/73

Abstract: A metal-oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region of a first conductivity type. The MOSFET additionally include a body region of a second conductivity type, where the body region underlies at least a portion of the source region and the drain region. The MOSFET further includes a buried region of the first conductivity type, where the buried region is disposed between the body region and a substrate, where the buried region is configured to reduce a capacitance between the source region and the drain region in response to an indicated voltage applied between the body region and the buried region.

公开(公告)号：US20230141865A1

公开(公告)日：2023-05-11

申请号：US18049543

申请日：2022-10-25

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Daniel Piedra ,  Leonard Shtargot ,  F. Jacob Steigerwald

IPC: H01L21/02 ,  H01L21/683

CPC classification number: H01L21/0254 ,  H01L21/683 ,  H01L21/0262

Abstract: A lateral GaN superjunction transistor or switching device that is configured to have higher breakdown voltage and lower on-resistance as compared to other GaN-based switching devices. The lateral GaN superjunction transistor includes a heavily doped buried implant region (hereinafter, “buried implant region”) in the substrate underlying the transistor that operates as backside field plate (BFP) to control or reduce gate-drain electric fields at the surface of the transistor, thereby enabling the transistor to operate at higher voltages while reducing charge trapping and breakdown effects. The lateral GaN superjunction transistor operates similarly to a vertical silicon superjunction FET to enable operation of the transistor at higher voltages than other GaN or semiconductor devices, such as to enable the construction of faster or higher power electronic circuits.

公开(公告)号：US20240405105A1

公开(公告)日：2024-12-05

申请号：US18204095

申请日：2023-05-31

Applicant: Analog Devices, Inc.

Inventor： F. Jacob Steigerwald ,  James G. Fiorenza ,  Guanghai Ding ,  Susan L. Feindt ,  Pengfei Wu ,  Clifford Alan King

IPC: H01L29/737 ,  H01L21/84 ,  H01L27/12 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66

Abstract: Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and/or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

公开(公告)号：US20200286997A1

公开(公告)日：2020-09-10

申请号：US16293464

申请日：2019-03-05

Applicant: Analog Devices, Inc.

Inventor： Pengfei Wu ,  Susan L. Feindt ,  F. Jacob Steigerwald

IPC: H01L29/10 ,  H01L29/73 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L27/07 ,  H01L21/74

Abstract: A metal-oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region of a first conductivity type. The MOSFET additionally include a body region of a second conductivity type, where the body region underlies at least a portion of the source region and the drain region. The MOSFET further includes a buried region of the first conductivity type, where the buried region is disposed between the body region and a substrate, where the buried region is configured to reduce a capacitance between the source region and the drain region in response to an indicated voltage applied between the body region and the buried region.