Invention Grant
- Patent Title: Sram bit cell retention
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Application No.: US16931870Application Date: 2020-07-17
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Publication No.: US11152046B1Publication Date: 2021-10-19
- Inventor: Jaroslav Raszka , Shahzad Nazar , Jaemyung Lim , Mohamed H. Abu-Rahma , Victor Zyuban
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Kowert, Hood, Munyon, Rankin & Goetzel, P.C.
- Agent Gareth M. Sampson
- Main IPC: G11C11/413
- IPC: G11C11/413 ; G11C8/12 ; G11C5/14

Abstract:
A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.
Information query
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