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公开(公告)号：US20220028479A1
公开(公告)日：2022-01-27
申请号：US17402915
申请日：2021-08-16
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Mohamed H. Abu-Rahma , Amrinder S. Barn
IPC: G11C29/50 , G11C11/419 , G11C11/409 , G11C29/12
Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
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公开(公告)号：US20240231758A1
公开(公告)日：2024-07-11
申请号：US18417868
申请日：2024-01-19
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Bharan Giridhar , Mohamed H. Abu-Rahma , Ajay Bhatia , Mayur V. Joshi , Yildiz Sinangil , Aravind Kandala
CPC classification number: G06F7/5443 , G06F7/523 , G06F17/15 , H03M1/46 , G06N20/00
Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.
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公开(公告)号：US20230298996A1
公开(公告)日：2023-09-21
申请号：US17655699
申请日：2022-03-21
Applicant: Apple Inc.
Inventor： Mohamed H. Abu-Rahma , Antonietta Oliva , Ajay Bhatia , Shahzad Nazar
IPC: H01L23/528 , H01L27/11
CPC classification number: H01L23/528 , H01L27/1104 , H01L27/1116
Abstract: Various implementations of backside and topside routing of bitlines and wordlines in memory arrays are disclosed. Bitlines in backside and topside metal layers may be alternated between adjacent bit cells in a memory array. Alternating the location of the bitlines between bit cells in the memory array may reduce bitline capacitance in a memory array. Placing wordlines in backside metal layers may allow dual wordlines to be implemented across a span of bit cells in a memory array. The dual wordlines may be alternately connected to adjacent bit cells, thereby allowing selective toggling of bit cells based on the wordline transmitting a control signal.
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公开(公告)号：US11688486B2
公开(公告)日：2023-06-27
申请号：US17402915
申请日：2021-08-16
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Mohamed H. Abu-Rahma , Amrinder S. Barn
IPC: G11C5/14 , G11C29/50 , G11C11/419 , G11C29/12 , G11C11/409
CPC classification number: G11C29/50016 , G11C11/409 , G11C11/419 , G11C29/12005 , G11C2029/5004
Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
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公开(公告)号：US11004482B1
公开(公告)日：2021-05-11
申请号：US16784030
申请日：2020-02-06
Applicant: Apple Inc.
Inventor： Jaemyung Lim , Jiangyi Li , Mohamed H. Abu-Rahma , Shahzad Nazar , Jaroslav Raszka
Abstract: Memory circuits used in computer systems may have different operating modes. In a retention mode, a voltage level of an array power supply node coupled to memory cells included in the memory circuit is reduced to a level sufficient to retain data, but not to perform read and write operations to the memory cells. A power converter circuit may be configured to generate the retention voltage level, and adjust the retention voltage level using a leakage current of dummy memory cells included in the memory circuit.
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Patent Agency Ranking
公开(公告)号：US11914973B2
公开(公告)日：2024-02-27
申请号：US16953093
申请日：2020-11-19
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Bharan Giridhar , Mohamed H. Abu-Rahma , Ajay Bhatia , Mayur V. Joshi , Yildiz Sinangil , Aravind Kandala
CPC classification number: G06F7/5443 , G06F7/523 , G06F17/15 , H03M1/46 , G06N20/00
Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of the global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit.
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公开(公告)号：US11152046B1
公开(公告)日：2021-10-19
申请号：US16931870
申请日：2020-07-17
Applicant: Apple Inc.
Inventor： Jaroslav Raszka , Shahzad Nazar , Jaemyung Lim , Mohamed H. Abu-Rahma , Victor Zyuban
IPC: G11C11/413 , G11C8/12 , G11C5/14
Abstract: A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.
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公开(公告)号：US20210142863A1
公开(公告)日：2021-05-13
申请号：US16677470
申请日：2019-11-07
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Mohamed H. Abu-Rahma , Amrinder S. Barn
IPC: G11C29/50 , G11C11/419 , G11C11/409 , G11C29/12
Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.
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公开(公告)号：US20240107738A1
公开(公告)日：2024-03-28
申请号：US18448634
申请日：2023-08-11
Applicant: Apple Inc.
Inventor： Saurabh P. Sinha , Shahzad Nazar , Xin Miao , Emre Alptekin
IPC: H10B10/00
CPC classification number: H10B10/125 , H10B10/18
Abstract: A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.
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公开(公告)号：US20220156045A1
公开(公告)日：2022-05-19
申请号：US16953093
申请日：2020-11-19
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Bharan Giridhar , Mohamed H. Abu-Rahma , Ajay Bhatia , Mayur V. Joshi , Yildiz Sinangil , Aravind Kandala
Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.
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