Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.