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    Apparatuses and methods for detecting a row hammer attack with a bandpass filter
    1.
    发明授权
    Apparatuses and methods for detecting a row hammer attack with a bandpass filter 有权

    公开(公告)号：US10658025B2

    公开(公告)日：2020-05-19

    申请号：US16545489

    申请日：2019-08-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yutaka Ito

    IPC: G11C11/24 ,  G11C11/4099 ,  G11C11/408 ,  G11C7/24 ,  G11C11/406 ,  G11C7/02

    Abstract: Apparatuses and methods for executing row hammer (RH) refresh are described. An example apparatus includes a RH control circuit to provide a row hammer address, and a refresh control circuit to perform a RH refresh operation on a memory address array related to the RH address. The RH control circuit includes first latches each to store an old row address used to access the memory and second latches provided correspondingly to the first latches each set to a state indicating whether the old row address stored in one of the first latches is valid. The RH control circuit further including a signal generator configured to assert a sample signal when a new row address to be used to access the memory array matches the old row address stored in any one of the first latches is valid based on a state of one of the second latches.

    Apparatus and methods for triggering row hammer address sampling
    2.
    发明授权
    Apparatus and methods for triggering row hammer address sampling 有权

    公开(公告)号：US10573370B2

    公开(公告)日：2020-02-25

    申请号：US16025844

    申请日：2018-07-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yutaka Ito ,  Yuan He

    IPC: G11C8/00 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4076

    Abstract: Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number. The filter circuit further includes a logic gate configured to pass one of the pulses of the clock signal responsive to the output signal from the control circuit being enabled and filter another of the pulses responsive to the output signal from the control circuit being not enabled.

    Systems and methods for testing a semiconductor memory device having a reference memory array
    3.
    发明授权
    Systems and methods for testing a semiconductor memory device having a reference memory array 有权

    公开(公告)号：US10366772B2

    公开(公告)日：2019-07-30

    申请号：US15684756

    申请日：2017-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Yuan He ,  Yutaka Ito

    IPC: G11C29/38 ,  G11C29/44 ,  G11C29/12 ,  G11C29/18 ,  G11C29/24 ,  G11C11/401

    Abstract: Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first bit-line and a plurality of first memory cells coupled to the first bit-line; a second memory cell array having a second bit-line and a plurality of second memory cells coupled to the second bit-line, the number of second memory cells being smaller than that of the first memory cells; a sense amplifier coupled to the first bit-line and a first end of the second bit-line; a word decoder configured to operate the second memory cells responsive to a first test signal; and a transistor coupled to a second end of the second bit-line and operated by a second test signal.

    APPARATUS AND METHODS FOR REFRESHING MEMORY
    4.
    发明申请
    APPARATUS AND METHODS FOR REFRESHING MEMORY 审中-公开

    公开(公告)号：US20190139599A1

    公开(公告)日：2019-05-09

    申请号：US16237291

    申请日：2018-12-31

    Applicant: Micron Technology, Inc.

    Inventor： Yutaka Ito ,  Yuan He

    IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

    Abstract: Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch that stores a row address; and a time based sampling circuit. The time based sampling circuit includes: a sampling timing generator that provides a timing signal of sampling a row address; and a plurality of bank sampling circuits, wherein each bank sampling circuit of the bank sampling circuits is included in a corresponding memory bank of the memory banks and provides a sampling signal to the latch in the corresponding memory bank responsive to the timing signal of sampling the row address; and an interval measurement circuit that receives an oscillation signal, measures an interval of a row hammer refresh execution based on a cycle of the oscillation signal, and further provides a steal rate timing signal for adjusting a steal rate to the sampling timing generator.

    MULTI CHANNEL MEMORY WITH FLEXIBLE CODE-LENGTH ECC
    5.
    发明申请
    MULTI CHANNEL MEMORY WITH FLEXIBLE CODE-LENGTH ECC 有权
    具有灵活代码长度ECC的多通道存储器

    公开(公告)号：US20170077955A1

    公开(公告)日：2017-03-16

    申请号：US14852232

    申请日：2015-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Yuan He ,  Yutaka Ito

    IPC: H03M13/29 ,  H03M13/00 ,  G06F11/10

    CPC classification number: H03M13/11 ,  H03M13/05 ,  H03M13/2906 ,  H03M13/611 ,  H03M13/616 ,  H03M13/6508

    Abstract: Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ECC) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ECC control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. The fourth input/output nodes of the first ECC control circuit are coupled respectively to the first input/output nodes of the first memory cell array. The fifth input/output nodes of the first ECC are coupled respectively to the second input/output nodes of the second memory cell array.

    Abstract translation: 描述了用于在多个通道上从存储器进行数据的纠错和检测的装置和方法。 一种示例性装置包括：包括第一输入/输出节点的第一存储单元阵列; 包括第二输入/输出节点和第三输入/输出节点的第二存储单元阵列; 包括第四输入/输出节点和第五输入/输出节点的第一纠错码（ECC）控制电路; 以及包括分别耦合到第二存储单元阵列的第三输入/输出节点的第六输入/输出节点的第二ECC控制电路。 第一ECC控制电路的第四输入/输出节点分别耦合到第一存储单元阵列的第一输入/输出节点。 第一ECC的第五输入/输出节点分别耦合到第二存储单元阵列的第二输入/输出节点。

    POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS
    8.
    发明申请
    POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS 有权
    节能存储器，系统和方法

    公开(公告)号：US20140247680A1

    公开(公告)日：2014-09-04

    申请号：US14277443

    申请日：2014-05-14

    Applicant: Micron Technology, Inc.

    Inventor： Yutaka Ito ,  Masayoshi Nomura ,  Keiichiro Abe

    IPC: G11C5/14

    CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C2211/4067 ,  G11C2211/4068

    Abstract: Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change between refresh operations of the memory device. Other embodiments including additional apparatus, systems, and methods are described.

    Abstract translation: 一些实施例包括电压发生器，用于产生电压以施加到用于访问存储器件的存储器单元的线，其中在存储器单元未被访问时将电压施加到线路;以及功率控制器， 电压在存储器件的刷新操作之间改变。 描述包括附加装置，系统和方法的其他实施例。

    APPARATUSES AND METHODS FOR MULTIPLE ROW HAMMER REFRESH ADDRESS SEQUENCES
    10.
    发明申请
    APPARATUSES AND METHODS FOR MULTIPLE ROW HAMMER REFRESH ADDRESS SEQUENCES 有权

    公开(公告)号：US20210350844A1

    公开(公告)日：2021-11-11

    申请号：US17443056

    申请日：2021-07-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Masaru Morohashi ,  Ryo Nagoshi ,  Yuan He ,  Yutaka Ito

    IPC: G11C11/406

    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

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