A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.