Invention Grant
- Patent Title: FinFET semiconductor device having source/drain contact(s) separated by airgap spacer(s) from the gate stack(s) to reduce parasitic capacitance
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Application No.: US16511258Application Date: 2019-07-15
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Publication No.: US11152486B2Publication Date: 2021-10-19
- Inventor: Cheng-Yu Yang , Kai-Hsuan Lee , Wei-Yang Lee , Fu-Kai Yang , Yen-Ming Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/088 ; H01L29/40 ; H01L29/417

Abstract:
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first gate stack, a second gate stack, a first source/drain feature disposed between the first and second gate stacks, and a source/drain contact over and electrically coupled to the first source/drain feature. The source/drain contact is spaced apart from each of the first and second gate stacks by an inner spacer disposed on sidewalls of the source/drain contact, a first air gap, a first gate spacer, and a second air gap separated from the first air gap by the first gate spacer.
Public/Granted literature
- US20210020757A1 Semiconductor Devices with Reduced Parasitic Capacitance Public/Granted day:2021-01-21
Information query
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