公开(公告)号：US11856743B2

公开(公告)日：2023-12-26

申请号：US17234201

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Hsuan Lee ,  Chia-Ta Yu ,  Cheng-Yu Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H10B10/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L21/027 ,  H01L21/306 ,  H01L21/311 ,  H01L29/66 ,  H01L29/165

CPC分类号： H10B10/12 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66636 ,  H10B10/18 ,  H01L21/823814 ,  H01L29/165

摘要： A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

公开(公告)号：US20230067455A1

公开(公告)日：2023-03-02

申请号：US17460569

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC分类号： H01L27/11597 ,  H01L27/11587 ,  H01L29/06 ,  H01L29/78

摘要： A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

公开(公告)号：US20230008128A1

公开(公告)日：2023-01-12

申请号：US17678554

申请日：2022-02-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sai-Hooi Yeong ,  Kai-Hsuan Lee ,  Chi On Chui

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/311

摘要： A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

公开(公告)号：US20220310445A1

公开(公告)日：2022-09-29

申请号：US17325477

申请日：2021-05-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC分类号： H01L21/768 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L23/522

摘要： In an embodiment, a device includes: a source/drain region adjoining a channel region of a substrate; a contact etch stop layer on the source/drain region; a first source/drain contact extending through the contact etch stop layer, the first source/drain contact connected to the source/drain region; a gate structure on the channel region; a gate contact connected to the gate structure; and a contact spacer around the gate contact, where the contact spacer, the gate structure, the contact etch stop layer, and the substrate collectively define a void between the gate structure and the first source/drain contact.

公开(公告)号：US11189706B2

公开(公告)日：2021-11-30

申请号：US16788184

申请日：2020-02-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien Ning Yao ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Wei-Yang Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/417

摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin formed on a substrate; and a gate structure disposed over a channel region of the semiconductor fin, the gate structure including a gate dielectric layer and a gate electrode, wherein the gate dielectric layer includes a bottom portion and a side portion, and the gate electrode is separated from the side portion of the gate dielectric layer by a first air gap.

公开(公告)号：US10811262B2

公开(公告)日：2020-10-20

申请号：US14996031

申请日：2016-01-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kai-Hsuan Lee ,  Jyh-Cherng Sheu ,  Sung-Li Wang ,  Cheng-Yu Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong

IPC分类号： H01L21/768 ,  H01L21/285 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L23/485

摘要： In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

公开(公告)号：US20200075417A1

公开(公告)日：2020-03-05

申请号：US16399553

申请日：2019-04-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Hsuan Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/06 ,  H01L21/764 ,  H01L21/3105

摘要： A method is provided for forming a device. The method includes forming a trench that exposes a source/drain (S/D) feature, wherein the S/D feature is separated from a metal gate structure (MG) by a gate spacer. The method further includes removing the gate spacer to form an air gap and forming a first dielectric layer in the trench, wherein the first dielectric layer partially fills the air gap. The method also includes forming a second dielectric layer over the first dielectric layer in the trench and forming a S/D contact over the S/D feature and the second dielectric layer, wherein the second dielectric layer is different from the first dielectric layer. After forming the S/D contact, the first dielectric layer is removed to extend the air gap; and after removing the first dielectric layer, a third dielectric layer is formed to seal the air gap.

公开(公告)号：US09496264B2

公开(公告)日：2016-11-15

申请号：US14621814

申请日：2015-02-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

发明人： Kai-Hsuan Lee ,  Cheng-Yu Yang ,  Hsiang-Ku Shen ,  Han-Ting Tsai ,  Yimin Huang

IPC分类号： H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L21/335 ,  H01L29/207 ,  H01L29/36 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/266 ,  H01L29/161 ,  H01L29/49

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/161 ,  H01L29/267 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate. The semiconductor device structure also includes a first doped structure over the semiconductor substrate and adjacent to the first gate stack. The first doped structure includes a III-V compound semiconductor material and a dopant. The semiconductor device structure further includes a second doped structure over the semiconductor substrate and adjacent to the second gate stack. The second doped structure includes the III-V compound semiconductor material and the dopant. One of the first doped structure and the second doped structure is an n-type semiconductor structure, and the other one of the first doped structure and the second doped structure is a p-type semiconductor structure.

摘要翻译： 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底和半导体衬底上的第一栅极堆叠和第二栅极堆叠。 半导体器件结构还包括在半导体衬底上并与第一栅极叠层相邻的第一掺杂结构。 第一掺杂结构包括III-V族化合物半导体材料和掺杂剂。 半导体器件结构还包括在半导体衬底上并与第二栅极堆叠相邻的第二掺杂结构。 第二掺杂结构包括III-V族化合物半导体材料和掺杂剂。 第一掺杂结构和第二掺杂结构之一是n型半导体结构，第一掺杂结构和第二掺杂结构中的另一个是p型半导体结构。

公开(公告)号：US12119259B2

公开(公告)日：2024-10-15

申请号：US17325477

申请日：2021-05-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L21/76831 ,  H01L21/76816 ,  H01L21/823475 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66795

摘要： In an embodiment, a device includes: a source/drain region adjoining a channel region of a substrate; a contact etch stop layer on the source/drain region; a first source/drain contact extending through the contact etch stop layer, the first source/drain contact connected to the source/drain region; a gate structure on the channel region; a gate contact connected to the gate structure; and a contact spacer around the gate contact, where the contact spacer, the gate structure, the contact etch stop layer, and the substrate collectively define a void between the gate structure and the first source/drain contact.

公开(公告)号：US20240332084A1

公开(公告)日：2024-10-03

申请号：US18738707

申请日：2024-06-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Hsuan Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC分类号： H01L21/8234 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

摘要： A method includes providing a workpiece including a gate structure (MG), a first spacer along a sidewall of the MG, a second spacer along a sidewall of the first spacer, and a source/drain (S/D) feature adjacent to the second spacer. The method further includes forming a contact trench over the S/D feature, removing the second spacer to form an air gap between the MG and the S/D feature, depositing a first dielectric layer over the S/D feature and partially filling the air gap, removing a portion of the first dielectric layer to expose a central portion of a top surface of the S/D feature while a side portion of the top surface of the S/D feature remains under the first dielectric layer, forming an S/D contact in the contact trench, removing the first dielectric layer to extend the air gap, and depositing a second dielectric layer over the air gap.