Invention Grant
- Patent Title: Gate-all-around structure with dummy pattern top in channel region and methods of forming the same
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Application No.: US16547026Application Date: 2019-08-21
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Publication No.: US11152488B2Publication Date: 2021-10-19
- Inventor: Ta-Chun Lin , Kuo-Hua Pan , Jhon Jhy Liaw
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/49 ; H01L21/8238 ; H01L29/786 ; H01L21/28

Abstract:
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a nanostructure disposed over a substrate, wherein the nanostructure includes a plurality of semiconductor layers separated vertically from each other and a dummy pattern layer including dielectric material disposed over and separated vertically from a top semiconductor layer of the plurality of semiconductor layers. The exemplary semiconductor device also comprises a gate structure disposed over a channel region, wherein the gate structure wraps around each of the plurality of semiconductor layers and the dummy pattern layer of the nanostructure.
Public/Granted literature
- US20210057544A1 Gate-All-Around Structure with Dummy Pattern Top in Channel Region and Methods of Forming the Same Public/Granted day:2021-02-25
Information query
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