Invention Grant
- Patent Title: Techniques to dynamically enable and disable accelerator devices in compute environments
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Application No.: US15719276Application Date: 2017-09-28
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Publication No.: US11157064B2Publication Date: 2021-10-26
- Inventor: Bharat S. Pillilli , Eswaramoorthi Nallusamy , Ramamurthy Krithivas , Vivek Garg , Venkatesh Ramamurthy
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Kacvinsky Daisak Bluni PLLC
- Main IPC: G06F1/3287
- IPC: G06F1/3287 ; G06F1/28 ; G06F1/26

Abstract:
Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.
Public/Granted literature
- US20190094946A1 TECHNIQUES TO DYNAMICALLY ENABLE AND DISABLE ACCELERATOR DEVICES IN COMPUTE ENVIRONMENTS Public/Granted day:2019-03-28
Information query
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