公开(公告)号：US11645159B2

公开(公告)日：2023-05-09

申请号：US16947133

申请日：2020-07-20

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy

IPC: G06F11/14 ,  G06F9/4401

CPC classification number: G06F11/1441 ,  G06F9/4403 ,  G06F9/4416

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

公开(公告)号：US11157064B2

公开(公告)日：2021-10-26

申请号：US15719276

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy ,  Ramamurthy Krithivas ,  Vivek Garg ,  Venkatesh Ramamurthy

IPC: G06F1/3287 ,  G06F1/28 ,  G06F1/26

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to send a power operation initiation indication to the accelerator device via the subset of the plurality of interconnects, the power operation initiation indication to indicate a power operation to be performed on one or more infrastructure devices, receive a response the accelerator device, the response to indicate to the processor that the accelerator is ready for the power operation, and ucause the power operation to be performed on the accelerator device, the power operation to enable or disable power for the one or more of the infrastructure devices.

公开(公告)号：US12045135B2

公开(公告)日：2024-07-23

申请号：US18312759

申请日：2023-05-05

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy

IPC: G06F11/14 ,  G06F9/4401

CPC classification number: G06F11/1441 ,  G06F9/4403 ,  G06F9/4416

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

公开(公告)号：US20180349137A1

公开(公告)日：2018-12-06

申请号：US15613519

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy ,  Mahesh S. Natu

IPC: G06F9/30 ,  G06F9/44

Abstract: Embodiments of processors, methods, and systems for reconfiguring a processor without a system reset are described. In an embodiment, a processor includes configuration storage, shadow configuration storage, trigger storage, and a trigger circuit. The trigger circuit is to cause, based on trigger storage content, shadow configuration storage content to be copied to the configuration storage.

公开(公告)号：US12204912B2

公开(公告)日：2025-01-21

申请号：US17384447

申请日：2021-07-23

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Johan Van De Groenendaal

IPC: G06F9/4401 ,  G06F13/20 ,  G06F13/42

Abstract: Apparatus and methods for booting and using a single CPU socket as a multi-CPU partitioned platform. The single CPU socket includes a plurality of core tiles that a partitioned into a plurality of virtual clusters comprising CPU sub-sockets. Each of the CPU sub-sockets in coupled to an Input-Output (IO) tile having an integrated boot support block and comprising a plurality of IO interfaces including at least one IO interface configured to receive boot signals for booting the sub-sockets and an IO interface to access boot firmware stored in a firmware storage device coupled to the IO interface. The integrated boot support block is configured to facilitate booting of each of the plurality of CPU sub-sockets using a shared set of boot resources coupled to the plurality of IO interfaces.

公开(公告)号：US12164907B2

公开(公告)日：2024-12-10

申请号：US17133462

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Johan Van De Groenendaal

IPC: G06F9/44 ,  G06F8/656 ,  G06F21/57

Abstract: Examples described herein a firmware update device to execute a second firmware, in place of execution of a first firmware, in response to an instruction that causes the firmware update device to execute the second firmware, wherein the second firmware is copied to a buffer prior to execution of the instruction. In some examples, one or more processors are to execute the instruction that causes the firmware update device to execute the second firmware. In some examples, prior to execution of the instruction, a device root of trust is also to validate the second firmware.

公开(公告)号：US20190205042A1

公开(公告)日：2019-07-04

申请号：US15856780

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Phani Kumar Kandula ,  Bharat S. Pillilli ,  Suresh Chemudupati ,  Yi-Feng Liu

IPC: G06F3/06 ,  G06F9/4401

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0685 ,  G06F9/4403

Abstract: An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.

公开(公告)号：US11803643B2

公开(公告)日：2023-10-31

申请号：US16785266

申请日：2020-02-07

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy

IPC: G06F21/57 ,  G06F13/42 ,  G06F9/4401

CPC classification number: G06F21/575 ,  G06F9/4401 ,  G06F9/4406 ,  G06F13/4282

Abstract: Examples described herein provide a hardware-software interface solution reads the boot code in segments into a buffer. A given boot code segment is stored in the buffer. A second buffer can be written-to with another boot code segment while the boot code segment in the buffer is read-from. A central processing unit (CPU) socket provides coordination such that one or more CPU sockets have copied the segment before permitting the segment to be overwritten in the buffer.

公开(公告)号：US10761938B2

公开(公告)日：2020-09-01

申请号：US15282643

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy

IPC: G06F11/14 ,  G06F9/4401

Abstract: A system for granular reset management without reboot is disclosed. The system may include a subsystem, a processor including a reset management circuit coupled to the subsystem. The reset management circuit may include circuitry to receive a command to reset the subsystem, determine whether the subsystem can be reset without performing a system wide reboot, and based on a determination that the subsystem can be reset without performing a system wide reboot, block the use of the subsystem, drain the subsystem, and reset the subsystem. Circuity and method are also disclosed.

公开(公告)号：US20200175169A1

公开(公告)日：2020-06-04

申请号：US16785266

申请日：2020-02-07

Applicant: Intel Corporation

Inventor： Bharat S. Pillilli ,  Eswaramoorthi Nallusamy

IPC: G06F21/57 ,  G06F9/4401 ,  G06F13/42

Abstract: Examples described herein provide a hardware-software interface solution reads the boot code in segments into a buffer. A given boot code segment is stored in the buffer. A second buffer can be written-to with another boot code segment while the boot code segment in the buffer is read-from. A central processing unit (CPU) socket provides coordination such that one or more CPU sockets have copied the segment before permitting the segment to be overwritten in the buffer.