Invention Grant
- Patent Title: System and method for ESD protection
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Application No.: US16777292Application Date: 2020-01-30
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Publication No.: US11159014B2Publication Date: 2021-10-26
- Inventor: Adrien Benoit Ille , Claudia Kupfer , Gernot Langguth
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Slater Matsil, LLP
- Main IPC: H02H9/04
- IPC: H02H9/04

Abstract:
In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.
Public/Granted literature
- US20210242678A1 SYSTEM AND METHOD FOR ESD PROTECTION Public/Granted day:2021-08-05
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