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公开(公告)号：US20250141219A1
公开(公告)日：2025-05-01
申请号：US18931784
申请日：2024-10-30
Applicant: Infineon Technologies AG
Inventor： Mirko Scholz , Steffen Schumann , Gernot Langguth , Adrien Benoit Ille
IPC: H02H9/04
Abstract: In accordance with an embodiment, a device includes: a first supply rail; a second supply rail; an input/output terminal; an electrostatic discharge protection device comprising at least two stacked transistors coupled between the input/output terminal and a first one of the first supply rail or the second supply rail; and a trigger circuit coupled to the first supply rail and the second supply rail and configured to: detect an electrostatic discharge event at the input/output terminal based on a voltage of the first supply rail or a voltage of the second supply rail, and switch on the electrostatic discharge protection device in response to detecting the electrostatic discharge event.
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公开(公告)号：US11088542B1
公开(公告)日：2021-08-10
申请号：US16777195
申请日：2020-01-30
Applicant: Infineon Technologies AG
Inventor： Gernot Langguth , Adrien Benoit Ille , Steffen Schumann
Abstract: In accordance with an embodiment, a method for electrostatic discharge (ESD) protection includes: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; compensating a temperature dependency of the divided voltage to form a temperature compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamp circuit coupled between the plurality of circuit nodes based on the temperature compensated divided voltage and based on the transient detection signal.
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Patent Agency Ranking
公开(公告)号：US20210242678A1
公开(公告)日：2021-08-05
申请号：US16777292
申请日：2020-01-30
Applicant: Infineon Technologies AG
Inventor： Adrien Benoit Ille , Claudia Kupfer , Gernot Langguth
IPC: H02H9/04
Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.
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公开(公告)号：US11594878B2
公开(公告)日：2023-02-28
申请号：US17403407
申请日：2021-08-16
Applicant: Infineon Technologies AG
Inventor： Adrien Benoit Ille , Claudia Kupfer , Gernot Langguth
IPC: H02H9/04
Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.
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公开(公告)号：US20210376601A1
公开(公告)日：2021-12-02
申请号：US17403407
申请日：2021-08-16
Applicant: Infineon Technologies AG
Inventor： Adrien Benoit Ille , Claudia Kupfer , Gernot Langguth
IPC: H02H9/04
Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.
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公开(公告)号：US11159014B2
公开(公告)日：2021-10-26
申请号：US16777292
申请日：2020-01-30
Applicant: Infineon Technologies AG
Inventor： Adrien Benoit Ille , Claudia Kupfer , Gernot Langguth
IPC: H02H9/04
Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.
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公开(公告)号：US20210242677A1
公开(公告)日：2021-08-05
申请号：US16777195
申请日：2020-01-30
Applicant: Infineon Technologies AG
Inventor： Gernot Langguth , Adrien Benoit Ille , Steffen Schumann
Abstract: In accordance with an embodiment, a method for electrostatic discharge (ESD) protection includes: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; compensating a temperature dependency of the divided voltage to form a temperature compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamp circuit coupled between the plurality of circuit nodes based on the temperature compensated divided voltage and based on the transient detection signal.
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