中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.014 seconds)

    System and method for ESD protection
    1.
    发明授权
    System and method for ESD protection 有权

    公开(公告)号：US11594878B2

    公开(公告)日：2023-02-28

    申请号：US17403407

    申请日：2021-08-16

    Applicant: Infineon Technologies AG

    Inventor： Adrien Benoit Ille ,  Claudia Kupfer ,  Gernot Langguth

    IPC: H02H9/04

    Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.

    System and Method for ESD Protection
    2.
    发明申请
    System and Method for ESD Protection 有权

    公开(公告)号：US20210376601A1

    公开(公告)日：2021-12-02

    申请号：US17403407

    申请日：2021-08-16

    Applicant: Infineon Technologies AG

    Inventor： Adrien Benoit Ille ,  Claudia Kupfer ,  Gernot Langguth

    IPC: H02H9/04

    Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.

    System and method for ESD protection
    3.
    发明授权
    System and method for ESD protection 有权

    公开(公告)号：US11159014B2

    公开(公告)日：2021-10-26

    申请号：US16777292

    申请日：2020-01-30

    Applicant: Infineon Technologies AG

    Inventor： Adrien Benoit Ille ,  Claudia Kupfer ,  Gernot Langguth

    IPC: H02H9/04

    Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.

    SYSTEM AND METHOD FOR TEMPERATURE COMPENSATED ESD PROTECTION
    4.
    发明申请
    SYSTEM AND METHOD FOR TEMPERATURE COMPENSATED ESD PROTECTION 有权

    公开(公告)号：US20210242677A1

    公开(公告)日：2021-08-05

    申请号：US16777195

    申请日：2020-01-30

    Applicant: Infineon Technologies AG

    Inventor： Gernot Langguth ,  Adrien Benoit Ille ,  Steffen Schumann

    IPC: H02H9/04 ,  H01L27/02 ,  H02H9/00

    Abstract: In accordance with an embodiment, a method for electrostatic discharge (ESD) protection includes: dividing a voltage between a plurality of circuit nodes using a voltage divider circuit to form a divided voltage; compensating a temperature dependency of the divided voltage to form a temperature compensated divided voltage; monitoring the voltage between the plurality of circuit nodes using a transient detection circuit to form a transient detection signal; and activating a clamp circuit coupled between the plurality of circuit nodes based on the temperature compensated divided voltage and based on the transient detection signal.

    ESD CLAMP ADJUSTMENT
    6.
    发明申请
    ESD CLAMP ADJUSTMENT 有权
    ESD钳位调整

    公开(公告)号：US20130077197A1

    公开(公告)日：2013-03-28

    申请号：US13676748

    申请日：2012-11-14

    Applicant: Infineon Technologies AG

    Inventor： Wolfgang Soldner ,  Gernot Langguth ,  Christian Russ ,  Harald Gossner

    IPC: H02H9/04

    CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L2924/0002 ,  H03K17/08122 ,  H01L2924/00

    Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.

    Abstract translation: 本公开的实施例涉及静电放电（ESD）保护技术。 例如，一些实施例包括可变电阻器，其选择性地将来自第一电路节点的输入ESD脉冲的功率分流到第二电路节点并远离半导体器件。 提供给可变电阻器的控制电压使得晶体管在只有亚阈值电流（如果有的话）流动的完全关闭模式之间改变; 其中最大量的电流流动的完全启动模式; 以及其中中间和时变量的电流流动的模拟模式。 特别地，模拟模式允许ESD保护装置比先前可实现的更精确地分流功率，使得ESD保护装置可以保护半导体器件免受ESD脉冲。

    SCR STRUCTURE FOR ESD PROTECTION IN SOI TECHNOLOGIES
    7.
    发明公开
    SCR STRUCTURE FOR ESD PROTECTION IN SOI TECHNOLOGIES 审中-公开

    公开(公告)号：US20230238454A1

    公开(公告)日：2023-07-27

    申请号：US17648985

    申请日：2022-01-26

    Applicant: Infineon Technologies AG

    Inventor： Gernot Langguth ,  Anton Boehm ,  Christian Cornelius Russ ,  Mirko Scholz

    IPC: H01L29/74 ,  H01L27/02 ,  H01L29/06 ,  H02H9/04

    CPC classification number: H01L29/7436 ,  H01L27/0259 ,  H01L29/0692 ,  H02H9/046 ,  H01L29/7408 ,  H01L27/0285 ,  H01L27/0292

    Abstract: In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

    ESD clamp adjustment
    10.
    发明授权
    ESD clamp adjustment 有权
    ESD钳位调整

    公开(公告)号：US08531807B2

    公开(公告)日：2013-09-10

    申请号：US13676748

    申请日：2012-11-14

    Applicant: Infineon Technologies AG

    Inventor： Wolfgang Soldner ,  Gernot Langguth ,  Christian Russ ,  Harald Gossner

    IPC: H02H9/00 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

    CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L2924/0002 ,  H03K17/08122 ,  H01L2924/00

    Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.

    Abstract translation: 本公开的实施例涉及静电放电（ESD）保护技术。 例如，一些实施例包括可变电阻器，其选择性地将来自第一电路节点的输入ESD脉冲的功率分流到第二电路节点并远离半导体器件。 提供给可变电阻器的控制电压使得晶体管在只有亚阈值电流（如果有的话）流动的完全关闭模式之间改变; 其中最大量的电流流动的完全启动模式; 以及其中中间和时变量的电流流动的模拟模式。 特别地，模拟模式允许ESD保护装置比先前可实现的更精确地分流功率，使得ESD保护装置可以保护半导体器件免受ESD脉冲。

Patent Agency Ranking