Invention Grant
- Patent Title: Fabrication method of integrated circuit semiconductor device
-
Application No.: US16744446Application Date: 2020-01-16
-
Publication No.: US11171038B2Publication Date: 2021-11-09
- Inventor: Namho Jeon , Joonyoung Choi , Jiyoung Kim , Junsoo Kim , Dongsoo Woo
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2019-0071068 20190614
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L27/12 ; H01L21/84 ; H01L27/108

Abstract:
A fabrication method of an integrated circuit semiconductor device includes: forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate; after forming the low dielectric pattern, forming a flow layer to bury the low dielectric pattern on the substrate; forming an epitaxial layer on the flow layer; and forming a transistor in the substrate comprising the low dielectric pattern buried by the flow layer and in the epitaxial layer.
Information query
IPC分类: