公开(公告)号：US12268042B2

公开(公告)日：2025-04-01

申请号：US17746247

申请日：2022-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: H01L21/00 ,  H10K10/50 ,  H10K19/00 ,  H10K85/20

Abstract: A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.

公开(公告)号：US12249651B2

公开(公告)日：2025-03-11

申请号：US17741219

申请日：2022-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/417

Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

公开(公告)号：US11329050B2

公开(公告)日：2022-05-10

申请号：US16993394

申请日：2020-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Dongsoo Woo ,  Wonchul Lee

IPC: H01L27/108

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

公开(公告)号：US11195836B2

公开(公告)日：2021-12-07

申请号：US16732925

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Junsoo Kim ,  Taehyun An ,  Dongsoo Woo ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.

公开(公告)号：US10964704B2

公开(公告)日：2021-03-30

申请号：US16550192

申请日：2019-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jung Lee ,  Joon-Seok Moon ,  Dongsoo Woo

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49

Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

公开(公告)号：US20240206157A1

公开(公告)日：2024-06-20

申请号：US18592121

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Dongsoo Woo ,  Wonchul Lee

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

公开(公告)号：US11616065B2

公开(公告)日：2023-03-28

申请号：US17090419

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US11380690B2

公开(公告)日：2022-07-05

申请号：US17186936

申请日：2021-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jung Lee ,  Joon-Seok Moon ,  Dongsoo Woo

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49

Abstract: A semicondcutor device, and a method of fabricating the semiconductor device including forming on a substrate a device isolation layer defining a plurality of active regions; and forming a plurality of gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming on the substrate a trench that intersects the active regions; forming a work-function control layer on a sidewall and a bottom surface of the trench; forming a conductive layer on the work-function control layer; sequentially forming a barrier layer and a source layer on the work-function control layer and the conductive layer, the source layer including a work-function control element; and diffusing the work-function control element from the source layer into an upper portion of the work-function control layer.

公开(公告)号：US11152365B2

公开(公告)日：2021-10-19

申请号：US15966554

申请日：2018-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namho Jeon ,  Jin-Seong Lee ,  Hyun-jung Lee ,  Dongsoo Woo ,  Donggyu Heo ,  Jaeho Hong

IPC: H01L27/105 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/108

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

公开(公告)号：US10818672B2

公开(公告)日：2020-10-27

申请号：US16405548

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/43 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/3215

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.