公开(公告)号：US12127394B2

公开(公告)日：2024-10-22

申请号：US18298230

申请日：2023-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

IPC: H10B12/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78

CPC classification number: H10B12/34 ,  H01L21/28026 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/7813 ,  H10B12/053 ,  H10B12/315

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

公开(公告)号：US11862476B2

公开(公告)日：2024-01-02

申请号：US17076025

申请日：2020-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L21/34 ,  H10B12/00 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/34 ,  H01L21/02 ,  H01L21/28 ,  H10B12/053 ,  H10B12/31 ,  H10B12/482

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US20230247824A1

公开(公告)日：2023-08-03

申请号：US18298230

申请日：2023-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HUIJUNG KIM ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

IPC: H01L29/94 ,  H01L29/423 ,  H01L29/78

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/053 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/7813

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

公开(公告)号：US11710788B2

公开(公告)日：2023-07-25

申请号：US17542969

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyujin Kim ,  Hui-Jung Kim ,  Junsoo Kim ,  Sangho Lee ,  Jae-Hwan Cho ,  Yoosang Hwang

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/8234 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H01L21/311 ,  H01L21/7621 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/7827 ,  H10B12/053

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

公开(公告)号：US11616065B2

公开(公告)日：2023-03-28

申请号：US17090419

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US11329137B2

公开(公告)日：2022-05-10

申请号：US16927463

申请日：2020-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

公开(公告)号：US20190296018A1

公开(公告)日：2019-09-26

申请号：US16185892

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US20190051652A1

公开(公告)日：2019-02-14

申请号：US15952308

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

公开(公告)号：US20240234500A9

公开(公告)日：2024-07-11

申请号：US18141990

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Yoo ,  Kihyung Ko ,  Junsoo Kim ,  Hyunsup Kim ,  Jihoon Cha

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775

Abstract: A semiconductor device may include an active pattern on a substrate; an isolation pattern on the substrate, the isolation pattern covering opposite sidewalls of the active pattern; a liner on the isolation pattern, a liner including a material different from the isolation pattern; a gate structure contacting an upper surface of the active pattern and an upper surface of the liner; and a plurality of channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the plurality of channels extending through the gate structure.

公开(公告)号：US11482277B2

公开(公告)日：2022-10-25

申请号：US17470641

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsoo Kim ,  Minwoo Kwon

IPC: G11C11/24 ,  G11C11/408 ,  H01L27/108

Abstract: An integrated circuit device includes a plurality of memory cells each including a channel region, a first sub-word line, a second sub-word line, and a storage element. A word line driving circuit is configured to drive the first and sub-word lines. The word line driving circuit includes a PMOS transistor, an NMOS transistor, a keeping NMOS transistor, and a first keeping PMOS transistor. A negative voltage is applied to a source of the NMOS transistor, the negative voltage is applied to a source of the keeping NMOS transistor, the first sub-word line is connected to a source of the first keeping PMOS transistor, the second sub-word line is connected to a drain of the first keeping PMOS transistor, and a negative voltage is applied to a gate of the first keeping PMOS transistor.