公开(公告)号：US11508733B2

公开(公告)日：2022-11-22

申请号：US16744871

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjun Noh ,  Junsoo Kim ,  Dongsoo Woo ,  Namho Jeon

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L27/108 ,  H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L29/51 ,  H01L21/3115 ,  H01L21/265 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3065

Abstract: An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

公开(公告)号：US11152365B2

公开(公告)日：2021-10-19

申请号：US15966554

申请日：2018-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namho Jeon ,  Jin-Seong Lee ,  Hyun-jung Lee ,  Dongsoo Woo ,  Donggyu Heo ,  Jaeho Hong

IPC: H01L27/105 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/108

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

公开(公告)号：US10818672B2

公开(公告)日：2020-10-27

申请号：US16405548

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/43 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/3215

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

公开(公告)号：US11189618B2

公开(公告)日：2021-11-30

申请号：US15966554

申请日：2018-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namho Jeon ,  Jin-Seong Lee ,  Hyun-jung Lee ,  Dongsoo Woo ,  Donggyu Heo ,  Jaeho Hong

IPC: H01L27/105 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/108

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

公开(公告)号：US20190027480A1

公开(公告)日：2019-01-24

申请号：US15920628

申请日：2018-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

IPC: H01L27/108

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

公开(公告)号：US11171038B2

公开(公告)日：2021-11-09

申请号：US16744446

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namho Jeon ,  Joonyoung Choi ,  Jiyoung Kim ,  Junsoo Kim ,  Dongsoo Woo

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L27/108

Abstract: A fabrication method of an integrated circuit semiconductor device includes: forming a plurality of low dielectric pattern apart from each other on a substrate, the plurality of low dielectric pattern having a lower dielectric constant than the substrate; after forming the low dielectric pattern, forming a flow layer to bury the low dielectric pattern on the substrate; forming an epitaxial layer on the flow layer; and forming a transistor in the substrate comprising the low dielectric pattern buried by the flow layer and in the epitaxial layer.

公开(公告)号：US10312243B2

公开(公告)日：2019-06-04

申请号：US15920628

申请日：2018-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-jung Lee ,  Dongsoo Woo ,  Jin-Seong Lee ,  Namho Jeon ,  Jaeho Hong

IPC: H01L29/43 ,  H01L29/49 ,  H01L27/108 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/51

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

公开(公告)号：US08901646B2

公开(公告)日：2014-12-02

申请号：US13727995

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namho Jeon ,  Min-chul Park ,  Seunguk Han

IPC: H01L29/66 ,  G11C11/408 ,  H01L27/108 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L27/088 ,  G11C11/4085 ,  G11C11/4087 ,  H01L27/0207 ,  H01L27/10897

Abstract: A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region.

Abstract translation: 半导体器件可以包括：衬底，其包括由器件隔离层限定的有源区，沿着第一方向在衬底上延伸并且彼此间隔开的栅电极，栅极突片沿与第一方向不同的第二方向延伸并连接相邻 栅极彼此间隔开，栅极突片彼此间隔开;以及第一接触插塞，其设置在由相邻的栅电极和相邻的栅极接线片限定的空间之下的有源区域上。 空间可以包括具有第一宽度的第一区域和具有小于第一宽度的第二宽度的第二区域，第一接触插塞可以设置在第二区域下方的有源区域上。