Invention Grant
- Patent Title: Plug and trench architectures for integrated circuits and methods of manufacture
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Application No.: US16329172Application Date: 2016-09-30
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Publication No.: US11171043B2Publication Date: 2021-11-09
- Inventor: Charles H. Wallace , Marvin Y. Paik , Hyunsoo Park , Mohit K. Haran , Alexander F. Kaplan , Ruth A. Brain
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2016/054799 WO 20160930
- International Announcement: WO2018/063330 WO 20180405
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/311 ; H01L23/522 ; H01L23/528
![Plug and trench architectures for integrated circuits and methods of manufacture](/abs-image/US/2021/11/09/US11171043B2/abs.jpg.150x150.jpg)
Abstract:
Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.
Public/Granted literature
- US20190206728A1 PLUG & TRENCH ARCHITECTURES FOR INTEGRATED CIRCUITS & METHODS OF MANUFACTURE Public/Granted day:2019-07-04
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