Invention Grant
- Patent Title: Technologies for preserving error correction capability in compute-in-memory operations
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Application No.: US16448126Application Date: 2019-06-21
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Publication No.: US11182242B2Publication Date: 2021-11-23
- Inventor: Chetan Chauhan , Wei Wu , Rajesh Sundaram , Shigeki Tomishima
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F11/30
- IPC: G06F11/30 ; G06F11/10 ; G06F11/07

Abstract:
Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.
Public/Granted literature
- US20190303237A1 TECHNOLOGIES FOR PRESERVING ERROR CORRECTION CAPABILITY IN COMPUTE-NEAR-MEMORY OPERATIONS Public/Granted day:2019-10-03
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