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公开(公告)号：US11687404B2
公开(公告)日：2023-06-27
申请号：US17530281
申请日：2021-11-18
Applicant: Intel Corporation
Inventor： Chetan Chauhan , Wei Wu , Rajesh Sundaram , Shigeki Tomishima
CPC classification number: G06F11/1044 , G06F11/0772 , G06F11/0793
Abstract: Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.
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公开(公告)号：US10860419B2
公开(公告)日：2020-12-08
申请号：US16236151
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Dinesh Somasekhar , Wei Wu , Shankar Ganesh Ramasubramanian , Vivek Kozhikkottu , Melin Dadual
Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.
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公开(公告)号：US10217493B2
公开(公告)日：2019-02-26
申请号：US15940811
申请日：2018-03-29
Applicant: INTEL CORPORATION
Inventor： Wei Wu , Shigeki Tomishima , Shih-Lien L. Lu
IPC: G06F13/00 , G11C7/06 , G06F13/16 , G06F13/40 , G06F13/42 , G11C7/10 , G11C11/406 , G11C11/4091 , G11C11/4093
Abstract: Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.
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公开(公告)号：US20180165152A1
公开(公告)日：2018-06-14
申请号：US15737202
申请日：2016-06-02
Applicant: Intel Corporation
Inventor： Helia Naeimi , Wei Wu , Shigeki Tomishima , Shih-Lien Lu
CPC classification number: G06F11/1048 , G11C11/1673 , G11C11/1675 , G11C29/52 , G11C2029/0411
Abstract: Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.
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公开(公告)号：US09992031B2
公开(公告)日：2018-06-05
申请号：US14040337
申请日：2013-09-27
Applicant: Intel Corporation
Inventor： Kevin Gotze , Gregory Iovino , David Johnston , Patrick Koeberl , Jiangtao Li , Wei Wu
CPC classification number: H04L9/34 , G09C1/00 , H04L9/0866 , H04L9/3278 , H04L2209/12
Abstract: Embodiments of an invention for using dark bits to reduce physically unclonable function (PUF) error rates are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and dark bit logic. The PUF cell array is to provide a raw PUF value. The dark bit logic is to select PUF cells to mark as dark bits and to generate a dark bit mask based on repeated testing of the PUF cell array.
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Patent Agency Ranking
公开(公告)号：US20180137005A1
公开(公告)日：2018-05-17
申请号：US15814336
申请日：2017-11-15
Applicant: Intel Corporation
Inventor： Wei Wu , Uksong Kang , Hussein Alameer , Rajat Agarwal , Kjersten E. Criss , John B. Halbert
CPC classification number: G06F11/1068 , G06F11/108 , G11C5/063 , G11C7/10 , G11C11/40618 , G11C11/4093 , G11C29/44 , G11C29/52 , G11C29/835 , G11C29/846
Abstract: In a memory system a multichip memory provides data redundancy for error recovery. The multichip memory can be an integrated circuit package with multiple memory dies or memory devices integrated with a common package. The multiple memory dies are coupled in a daisy chain, and can be a vertical stack or in a planar formation. The memory chip or chips at the end of the chain store parity data, and the other devices store data. The multichip memory includes XOR (exclusive OR) logic to compute parity to store in the redundant parity chips.
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公开(公告)号：US09965415B2
公开(公告)日：2018-05-08
申请号：US14975293
申请日：2015-12-18
Applicant: INTEL CORPORATION
Inventor： Wei Wu , Shigeki Tomishima , Shih-Lien L. Lu
CPC classification number: G06F13/28 , G06F13/1668 , G06F13/4027
Abstract: Provided are a memory device and a memory bank comprising a split local data bus, and a segmented global data bus coupled to local data bus. Provided also is a method comprising, receiving a signal from a split local data bus, and transmitting the signal to a segmented global data bus coupled to local data bus. Provided also is a computational device that includes the memory device and the memory bank, and optionally one or more of a display, a network interface, and a battery.
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公开(公告)号：US20170185476A1
公开(公告)日：2017-06-29
申请号：US14981649
申请日：2015-12-28
Applicant: Intel Corporation
Inventor： Wei Wu , Brian J. Hickmann , Dennis R. Bradford
CPC classification number: G06F11/1068 , G06F11/1012 , G11C29/52 , H03M13/13 , H03M13/15 , H03M13/1575 , H03M13/27 , H03M13/616
Abstract: An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity codes and error correction codes (ECCs); error correction logic to correct the errors detected by the error detection logic; and a matrix usable by both the error detection logic to detect the one or more errors and the error correction logic to correct the errors, the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region.
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公开(公告)号：US09514796B1
公开(公告)日：2016-12-06
申请号：US14751801
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Charles Augustine , Shigeki Tomishima , Wei Wu , Shih-Lien Lu , James W. Tschanz , Georgios Panagopoulos , Helia Naeimi
CPC classification number: G11C11/1675 , G11C11/1659 , G11C11/1677 , G11C11/1693 , G11C11/1697
Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.
Abstract translation: 描述了一种包括具有电阻存储单元的半导体芯片存储器阵列的装置。 该装置还包括比较器，用于将写入阵列的第一个字与存储在阵列中的第二个字进行比较，该第二个字由写入操作所指向的位置将第一个字写入数组。 该装置还包括用于迭代地写入一个或多个比特位置的电路，其中在每个连续的迭代中随着写入电流强度的增加而在第一个字和第二个字之间存在差异。
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公开(公告)号：US09251095B2
公开(公告)日：2016-02-02
申请号：US14339756
申请日：2014-07-24
Applicant: Intel Corporation
Inventor： David Champagne , Abhishek Tiwari , Wei Wu , Christopher J. Hughes , Sanjeev Kumar , Shih-Lien Lu
IPC: G06F12/10
CPC classification number: G06F12/1036 , G06F12/1009 , G06F12/1027 , G06F2212/681
Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.
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