Invention Grant
- Patent Title: Multi-level system memory with near memory capable of storing compressed cache lines
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Application No.: US15717939Application Date: 2017-09-28
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Publication No.: US11188467B2Publication Date: 2021-11-30
- Inventor: Israel Diamand , Alaa R. Alameldeen , Sreenivas Subramoney , Supratik Majumder , Srinivas Santosh Kumar Madugula , Jayesh Gaur , Zvika Greenfield , Anant V. Nori
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0846 ; G06F12/0811 ; G06F12/128 ; G06F12/121 ; G06F12/0886 ; G06F12/08

Abstract:
A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.
Public/Granted literature
- US20190095331A1 MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPRESSED CACHE LINES Public/Granted day:2019-03-28
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