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    Processor instructions for data compression and decompression
    1.
    发明授权
    Processor instructions for data compression and decompression 有权

    公开(公告)号：US12106104B2

    公开(公告)日：2024-10-01

    申请号：US17133328

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Christopher J. Hughes

    IPC: G06F9/30 ,  G06F12/0862 ,  H03M7/30

    CPC classification number: G06F9/30047 ,  G06F9/30145 ,  G06F12/0862 ,  H03M7/30 ,  G06F2212/602

    Abstract: A processor that includes compression instructions to compress multiple adjacent data blocks of uncompressed read-only data stored in memory into one compressed read-only data block and store the compressed read-only data block in multiple adjacent blocks in the memory is provided. During execution of an application to operate on the read-only data, one of the multiple adjacent blocks storing the compressed read-only block is read from memory, stored in a prefetch buffer and decompressed in the memory controller. In response to a subsequent request during execution of the application for an adjacent data block in the compressed read-only data block, the uncompressed adjacent block is read directly from the prefetch buffer.

    Selective error correction in memory to reduce power consumption
    2.
    发明授权
    Selective error correction in memory to reduce power consumption 有权
    内存中的选择性错误校正可降低功耗

    公开(公告)号：US08966345B2

    公开(公告)日：2015-02-24

    申请号：US13688028

    申请日：2012-11-28

    Applicant: Intel Corporation

    Inventor： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Shih-Lien L. Lu

    IPC: H03M13/00 ,  G06F11/08

    CPC classification number: G06F11/08 ,  G06F11/1052

    Abstract: Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory.

    Abstract translation: 本文描述了用于具有多种操作模式的存储器中的选择性误差校正的装置，方法，系统和装置的实施例。 在各种实施例中，错误校正块（例如，存储器控制器）可以被配置为基于从存储器的第二部分读取的对应的纠错码对存储器的第一部分读取的数据执行纠错，以及 计算和存储纠错码。 耦合到纠错块的控制块可以被配置为至少部分地基于存储器的当前操作模式来选择性地启用/禁用纠错块来执行纠错，并且计算和存储纠错码 。

    Two-level main memory hierarchy management
    3.
    发明授权
    Two-level main memory hierarchy management 有权

    公开(公告)号：US12271305B2

    公开(公告)日：2025-04-08

    申请号：US17214818

    申请日：2021-03-27

    Applicant: Intel Corporation

    Inventor： Sai Prashanth Muralidhara ,  Alaa R. Alameldeen ,  Rajat Agarwal ,  Wei P. Chen ,  Vivek Kozhikkottu

    IPC: G06F12/0802 ,  G06F3/06

    Abstract: A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and predicted cold pages in second level main memory. The cache line granularity movement is performed in a “swap” manner, that is, a hot cache line in the second level main memory is swapped with a cold cache line in first level main memory because data is stored in either first level main memory or second level main memory not in both first level main memory and second level main memory.

    Cache architecture using way ID to reduce near memory traffic in a two-level memory system
    5.
    发明授权
    Cache architecture using way ID to reduce near memory traffic in a two-level memory system 有权

    公开(公告)号：US10884927B2

    公开(公告)日：2021-01-05

    申请号：US15927715

    申请日：2018-03-21

    Applicant: Intel Corporation

    Inventor： Zhe Wang ,  Alaa R. Alameldeen

    IPC: G06F12/0811 ,  G06F12/0804

    Abstract: One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.

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