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    Programmable power management agent
    1.
    发明授权
    Programmable power management agent 有权

    公开(公告)号：US10761594B2

    公开(公告)日：2020-09-01

    申请号：US15623536

    申请日：2017-06-15

    Applicant: Intel Corporation

    Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

    IPC: G06F1/32 ,  G06F1/26 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/324

    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

    Memory controller for multi-level system memory with coherency unit
    2.
    发明授权
    Memory controller for multi-level system memory with coherency unit 有权

    公开(公告)号：US10204047B2

    公开(公告)日：2019-02-12

    申请号：US14671892

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Israel Diamand ,  Nir Misgav ,  Aravindh Anantaraman ,  Zvika Greenfield

    IPC: G06F12/0811

    Abstract: An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.

    CODE PREFETCH INSTRUCTION
    7.
    发明申请
    CODE PREFETCH INSTRUCTION 有权

    公开(公告)号：US20210342134A1

    公开(公告)日：2021-11-04

    申请号：US17033751

    申请日：2020-09-26

    Applicant: Intel Corporation

    Inventor： Ahmad Yasin ,  Lihu Rappoport ,  Jared W. Stark ,  Jeffrey Baxter ,  Israel Diamand ,  Pavel Fridman ,  Ibrahim Hur ,  Nir Tell

    IPC: G06F8/41

    Abstract: Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

    Dynamically programmable memory test traffic router
    8.
    发明授权
    Dynamically programmable memory test traffic router 有权

    公开(公告)号：US11042315B2

    公开(公告)日：2021-06-22

    申请号：US15940499

    申请日：2018-03-29

    Applicant: Intel Corporation

    Inventor： Lakshminarayana Pappu ,  Christopher E. Cox ,  Navneet Dour ,  Asaf Rubinstein ,  Israel Diamand

    IPC: G06F3/06 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/42

    Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

    Programmable power management agent
    9.
    发明授权
    Programmable power management agent 有权

    公开(公告)号：US09710054B2

    公开(公告)日：2017-07-18

    申请号：US14634777

    申请日：2015-02-28

    Applicant: Intel Corporation

    Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

    Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

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