Invention Grant
- Patent Title: Methods of forming multi-chip wafer level packages
-
Application No.: US16928003Application Date: 2020-07-14
-
Publication No.: US11189596B2Publication Date: 2021-11-30
- Inventor: Shuo-Mao Chen , Feng-Cheng Hsu , Han-Hsiang Huang , Hsien-Wen Liu , Shin-Puu Jeng , Hsiao-Wen Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/16 ; H01L23/538 ; H01L25/00 ; H01L21/56 ; H01L21/683 ; H01L23/31

Abstract:
Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
Public/Granted literature
- US20200343220A1 METHODS OF FORMING MULTI-CHIP WAFER LEVEL PACKAGES Public/Granted day:2020-10-29
Information query
IPC分类: