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公开(公告)号:US12224266B2
公开(公告)日:2025-02-11
申请号:US18501314
申请日:2023-11-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shin-Puu Jeng , Po-Yao Chuang , Shuo-Mao Chen
IPC: H01L25/065 , H01L21/56 , H01L23/31 , H01L23/538 , H01L25/00
Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.
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公开(公告)号:US20240379646A1
公开(公告)日:2024-11-14
申请号:US18780037
申请日:2024-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shin-Puu Jeng , Techi Wong , Po-Yao Chuang , Shuo-Mao Chen , Meng-Wei Chou
IPC: H01L25/18 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/065 , H01L27/01
Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.
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公开(公告)号:US12094810B2
公开(公告)日:2024-09-17
申请号:US18340387
申请日:2023-06-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chia-Kuei Hsu , Ming-Chih Yew , Po-Yao Lin , Shuo-Mao Chen , Feng-Cheng Hsu , Shin-Puu Jeng
IPC: H01L23/48 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/498 , H01L25/065 , H01L25/18
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/563 , H01L23/49838 , H01L24/81 , H01L25/0655 , H01L25/18 , H01L2224/81815
Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.
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公开(公告)号:US11728256B2
公开(公告)日:2023-08-15
申请号:US17808827
申请日:2022-06-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chia-Kuei Hsu , Ming-Chih Yew , Po-Yao Lin , Shuo-Mao Chen , Feng-Cheng Hsu , Shin-Puu Jeng
IPC: H01L23/48 , H01L23/498 , H01L21/48 , H01L21/56 , H01L23/00 , H01L25/065 , H01L25/18
CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/563 , H01L23/49838 , H01L24/81 , H01L25/0655 , H01L25/18 , H01L2224/81815
Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.
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公开(公告)号:US20220375843A1
公开(公告)日:2022-11-24
申请号:US17881981
申请日:2022-08-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor: Shin-Puu Jeng , Shuo-Mao Chen , Hsien-Wen Liu , Po-Yao Chuang , Feng-Cheng Hsu , Po-Yao Lin
IPC: H01L23/498 , H01L25/10 , H01L23/00 , H01L23/538 , H01L25/00 , H01L23/31
Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.
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公开(公告)号:US20220165587A1
公开(公告)日:2022-05-26
申请号:US17669184
申请日:2022-02-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Feng-Cheng Hsu , Shuo-Mao Chen , Jui-Pin Hung , Shin-Puu Jeng
IPC: H01L21/56 , H01L21/78 , H01L23/00 , H01L23/31 , H01L23/538 , H01L21/683 , H01L25/00
Abstract: An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.
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公开(公告)号:US20200343096A1
公开(公告)日:2020-10-29
申请号:US16928001
申请日:2020-07-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Feng-Cheng Hsu , Shuo-Mao Chen , Shin-Puu Jeng
IPC: H01L21/304 , H01L23/538 , H01L23/31 , H01L23/00 , H01L23/367 , H01L25/10 , H01L21/48 , H01L21/56 , H01L25/00 , H01L23/28 , H01L21/02 , H01L21/67 , H01L21/78 , H01L21/683 , B28D5/00 , H01L23/498
Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, a RDL structure, an underfill layer, a protection layer, and a cap. The TIV is aside the die. The encapsulant laterally encapsulates the die and the TIV. The RDL structure is electrically connected to the die. The underfill layer is disposed between the die and the RDL structure and laterally encapsulated by the encapsulant. The protection layer is overlying the die and the encapsulant. The cap covers a top surface of the TIV and laterally aside the protection layer. A top surface of the cap is higher than a top surface of the encapsulant and lower than a top surface of the protection layer.
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公开(公告)号:US20200286744A1
公开(公告)日:2020-09-10
申请号:US16881013
申请日:2020-05-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chia-Hsiang Lin , Feng-Cheng Hsu , Shuo-Mao Chen , Shin-Puu Jeng , Arunima Banerjee
IPC: H01L21/48 , H01L23/498 , H01L23/00 , H01L21/683
Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.
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公开(公告)号:US10475731B2
公开(公告)日:2019-11-12
申请号:US16371356
申请日:2019-04-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shuo-Mao Chen , Der-Chyang Yeh , Chiung-Han Yeh
IPC: H01L23/498 , H01L21/56 , H01L23/00 , H01L23/538 , H01L23/31
Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
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公开(公告)号:US10276551B2
公开(公告)日:2019-04-30
申请号:US15854762
申请日:2017-12-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Po-Yao Lin , Cheng-Yi Hong , Feng-Cheng Hsu , Shuo-Mao Chen , Shin-Puu Jeng , Shu-Shen Yeh , Kuang-Chun Lee
IPC: H01L23/053 , H01L23/12 , H01L25/18 , H01L23/538 , H01L21/48 , H01L21/56 , H01L23/24 , H01L25/00 , H01L23/31 , H01L23/373
Abstract: A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one warpage adjusting component, and an encapsulating material. The first semiconductor device is disposed on the redistribution structure. The second semiconductor devices are disposed on the redistribution structure and surround the first semiconductor device. The at least one warpage adjusting component is disposed on at least one of the second semiconductor devices. The encapsulating material encapsulates the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.
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