Invention Grant
- Patent Title: Gate-all-around devices with reduced parasitic capacitance
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Application No.: US16774278Application Date: 2020-01-28
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Publication No.: US11189617B2Publication Date: 2021-11-30
- Inventor: Peijie Feng , Ye Lu , Junjing Bao , Chenjie Tang
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, LL.P.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/06 ; H01L29/66 ; H01L29/08 ; H01L29/423 ; H01L29/10 ; H01L27/092 ; H01L29/49 ; H01L21/02 ; H01L21/8238 ; H01L21/027 ; H01L21/311 ; H01L21/306

Abstract:
Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.
Public/Granted literature
- US20210233911A1 GATE-ALL-AROUND DEVICES WITH REDUCED PARASITIC CAPACITANCE Public/Granted day:2021-07-29
Information query
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