Invention Grant
- Patent Title: Integration of a III-V device on a Si substrate
-
Application No.: US16550085Application Date: 2019-08-23
-
Publication No.: US11195767B2Publication Date: 2021-12-07
- Inventor: Amey Mahadev Walke , Liesbeth Witters , Niamh Waldron , Robert Langer , Bernardette Kunert
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC VZW
- Current Assignee: IMEC VZW
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP18194368 20180913
- Main IPC: H01L21/8258
- IPC: H01L21/8258 ; H01L29/66 ; H01L21/3105 ; H01L21/3065 ; H01L29/423 ; H01L21/308

Abstract:
A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.
Public/Granted literature
- US20200091003A1 Integration of a III-V Device on a Si Substrate Public/Granted day:2020-03-19
Information query
IPC分类: