公开(公告)号：US20210118724A1

公开(公告)日：2021-04-22

申请号：US16996413

申请日：2020-08-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/8249 ,  H01L27/07

Abstract: The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a SixGe1-x(100) substrate. The method includes: (a) providing a SixGe1-x(100) substrate, where x is from 0 to 1; (b) selecting a first region for forming therein a group IV device and a second region for forming therein a III-V device, the first and the second region each comprising a section of the SixGe1-x(100) substrate; (c) forming a trench isolation for at least the III-V device; (d) providing a SiyGe1-y(100) surface in the first region, where y is from 0 to 1; (e) at least partially forming the group IV device on the SiyGe1-y(100) surface in the first region; (f) forming a trench in the second region which exposes the SixGe1-x(100) substrate, the trench having a depth of at least 200 nm, at least 500 nm, at least 1 μm, usually at least 2 μm, such as 4 μm, with respect to the SiyGe1-y(100) surface in the first region; (g) growing a III-V material in the trench using aspect ratio trapping; and (h) forming the III-V device on the III-V material, the III-V device comprising at least one contact region at a height within 100 nm, 50 nm, 20 nm, usually 10 nm, of a contact region of the group IV device.

公开(公告)号：US20160336317A1

公开(公告)日：2016-11-17

申请号：US15152700

申请日：2016-05-12

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Anabela Veloso

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/7848

Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.

Abstract translation: 一种用于制造CMOS器件的方法包括提供在半导体基底层上外延生长锗层的半导体基底层，所述锗层的厚度高于临界厚度，使得锗层的上部应力松弛。 该方法还包括执行退火步骤，使锗层变薄并将锗层图案化成翅片结构或垂直线结构。 该方法还包括将鳍结构或垂直线结构横向嵌入介电层中，并提供覆盖第一区的掩蔽层，使第二区露出。 该方法还包括选择性地去除第二区域中的翅片结构或垂直线结构，直到主上表面，产生沟槽并通过在沟槽中外延生长一个或多个半导体层而在沟槽中生长突起。

公开(公告)号：US20160027780A1

公开(公告)日：2016-01-28

申请号：US14809089

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Jerome Mitard ,  Roger Loo ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/04 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/165 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物硅（CMOS）器件，更具体地涉及包括诸如n沟道金属氧化物 - 硅（NMOS）晶体管器件的锗沟道层的晶体管器件。 在一个方面，形成用于NMOS晶体管器件的锗沟道层的方法包括：提供具有由介电材料结构限定的侧壁并邻接在硅衬底的表面上并具有在表面上的沟槽中的种子层的沟槽，其中 种子层具有包括具有（111）取向的小平面的前表面。 该方法还包括在种子层上的沟槽中生长应变松弛缓冲层，其中应变松弛缓冲层包括硅锗。 该方法还包括在应变松弛缓冲层上生长包含锗（Ge）的沟道层。 在其他方面，诸如NMOS晶体管器件和CMOS器件的器件包括使用该方法制造的特征。

公开(公告)号：US20160027779A1

公开(公告)日：2016-01-28

申请号：US14808459

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Roger Loo ,  Jerome Mitard ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物 - 硅（CMOS）器件，更具体地涉及n沟道金属氧化物硅（nMOS）器件和p沟道金属氧化物（pMOS）器件，其是 在不同类型的菌株下。 在一个方面，一种方法包括在半导体衬底上的电介质层中提供沟槽，其中至少第一沟槽限定nMOS区域，并且第二沟槽限定pMOS区域，并且其中沟槽延伸穿过介电层并邻接表面 的基底。 该方法还包括在表面上的第一沟槽中生长第一籽晶层，并在第一沟槽和第二沟槽中生长共同的应变松弛缓冲层，其中常见的应变松弛缓冲层包括硅锗（SiGe）。 该方法还包括在第一和第二沟槽中以及共同的应变松弛缓冲层上生长包括锗（Ge）的公共沟道层。 第一种子层和公共应变松弛缓冲层的性质是预定的，使得公共沟道层处于拉伸应变或在nMOS区域中不受约束，并且在pMOS区域中具有压缩应变。 方面还包括使用该方法形成的装置。

公开(公告)号：US11387350B2

公开(公告)日：2022-07-12

申请号：US16719852

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Geert Eneman ,  Bartlomiej Pawlak ,  Liesbeth Witters ,  Geoffrey Pourtois

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

公开(公告)号：US11355618B2

公开(公告)日：2022-06-07

申请号：US17103031

申请日：2020-11-24

Applicant: IMEC VZW

Inventor： Abhitosh Vais ,  Liesbeth Witters ,  Yves Mols

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/737 ,  H01L21/306 ,  H01L29/205

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

公开(公告)号：US20170141199A1

公开(公告)日：2017-05-18

申请号：US15345782

申请日：2016-11-08

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Zheng Tao ,  Boon Teik Chan ,  Liesbeth Witters ,  Marc Schaekers ,  Antony Premkumar Peter ,  Silvia Armini

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/45 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L29/41791 ,  H01L21/02115 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

公开(公告)号：US09478544B2

公开(公告)日：2016-10-25

申请号：US14809089

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Jerome Mitard ,  Roger Loo ,  Liesbeth Witters

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/04

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/165 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a germanium channel layer, such as an n-channel metal-oxide-silicon (NMOS) transistor device. In one aspect, a method of forming a germanium channel layer for an NMOS transistor device comprises providing a trench having sidewalls defined by a dielectric material structure and abutting on a silicon substrate's surface, and growing a seed layer in the trench on the surface, where the seed layer has a front surface comprising facets having a (111) orientation. The method additionally includes growing a strain-relaxed buffer layer in the trench on the seed layer, where the strain-relaxed buffer layer comprises silicon germanium. The method further includes growing a channel layer comprising germanium (Ge) on the strain-relaxed buffer layer. In other aspects, devices, e.g., an NMOS transistor device and a CMOS device, includes features fabricated using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物硅（CMOS）器件，更具体地涉及包括诸如n沟道金属氧化物 - 硅（NMOS）晶体管器件的锗沟道层的晶体管器件。 在一个方面，形成用于NMOS晶体管器件的锗沟道层的方法包括提供具有由介电材料结构限定的侧壁并邻接在硅衬底表面上的侧壁的沟槽，以及在表面上的沟槽中生长晶种层， 种子层具有包括具有（111）取向的小平面的前表面。 该方法还包括在种子层上的沟槽中生长应变松弛缓冲层，其中应变松弛缓冲层包括硅锗。 该方法还包括在应变松弛缓冲层上生长包含锗（Ge）的沟道层。 在其他方面，诸如NMOS晶体管器件和CMOS器件的器件包括使用该方法制造的特征。

公开(公告)号：US09299563B2

公开(公告)日：2016-03-29

申请号：US14313928

申请日：2014-06-24

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Liesbeth Witters ,  Roger Loo

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/10 ,  H01L21/3065

CPC classification number: H01L21/02658 ,  H01L21/02587 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/1054

Abstract: The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer.

Abstract translation: 本发明涉及形成应变半导体结构的方法。 该方法包括提供应变松弛缓冲层，在应变松弛缓冲层上形成牺牲层，通过牺牲层形成浅沟槽隔离结构，去除牺牲层上的氧化物层的至少一部分，蚀刻通过牺牲层 使得应变松弛缓冲层的一部分被暴露，在应变松弛缓冲层的暴露部分上形成应变半导体结构。

公开(公告)号：US11557503B2

公开(公告)日：2023-01-17

申请号：US16996413

申请日：2020-08-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8249 ,  H01L27/07

Abstract: The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a SixGe1-x(100) substrate. The method includes: (a) providing a SixGe1-x(100) substrate, where x is from 0 to 1; (b) selecting a first region for forming therein a group IV device and a second region for forming therein a III-V device, the first and the second region each comprising a section of the SixGe1-x(100) substrate; (c) forming a trench isolation for at least the III-V device; (d) providing a SiyGe1-y(100) surface in the first region, where y is from 0 to 1; (e) at least partially forming the group IV device on the SiyGe1-y(100) surface in the first region; (f) forming a trench in the second region which exposes the SixGe1-x(100) substrate, the trench having a depth of at least 200 nm, at least 500 nm, at least 1 μm, usually at least 2 μm, such as 4 μm, with respect to the SiyGe1-y(100) surface in the first region; (g) growing a III-V material in the trench using aspect ratio trapping; and (h) forming the III-V device on the III-V material, the III-V device comprising at least one contact region at a height within 100 nm, 50 nm, 20 nm, usually 10 nm, of a contact region of the group IV device.