公开(公告)号：US20210358748A1

公开(公告)日：2021-11-18

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/778 ,  H01L29/66

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

公开(公告)号：US20180068898A1

公开(公告)日：2018-03-08

申请号：US15685137

申请日：2017-08-24

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L23/535

CPC classification number: H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

公开(公告)号：US20200328108A1

公开(公告)日：2020-10-15

申请号：US16844845

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Amey Mahadev Walke ,  Niamh Waldron ,  Nadine Collaert ,  Ming Zhao

IPC: H01L21/762 ,  H01L29/778 ,  H01L29/66 ,  H01L25/16

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.

公开(公告)号：US10163714B2

公开(公告)日：2018-12-25

申请号：US15685137

申请日：2017-08-24

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L23/535 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L27/02

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

公开(公告)号：US11557503B2

公开(公告)日：2023-01-17

申请号：US16996413

申请日：2020-08-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8249 ,  H01L27/07

Abstract: The present disclosure relates to a semi-conductor structure and method for co-integrating a III-V device with a group IV device on a SixGe1-x(100) substrate. The method includes: (a) providing a SixGe1-x(100) substrate, where x is from 0 to 1; (b) selecting a first region for forming therein a group IV device and a second region for forming therein a III-V device, the first and the second region each comprising a section of the SixGe1-x(100) substrate; (c) forming a trench isolation for at least the III-V device; (d) providing a SiyGe1-y(100) surface in the first region, where y is from 0 to 1; (e) at least partially forming the group IV device on the SiyGe1-y(100) surface in the first region; (f) forming a trench in the second region which exposes the SixGe1-x(100) substrate, the trench having a depth of at least 200 nm, at least 500 nm, at least 1 μm, usually at least 2 μm, such as 4 μm, with respect to the SiyGe1-y(100) surface in the first region; (g) growing a III-V material in the trench using aspect ratio trapping; and (h) forming the III-V device on the III-V material, the III-V device comprising at least one contact region at a height within 100 nm, 50 nm, 20 nm, usually 10 nm, of a contact region of the group IV device.

公开(公告)号：US20220254795A1

公开(公告)日：2022-08-11

申请号：US17650154

申请日：2022-02-07

Applicant: IMEC vzw

Inventor： Mihaela Ioana Popovici ,  Amey Mahadev Walke ,  Jan Van Houdt

IPC: H01L27/11507 ,  H01L49/02 ,  H01L29/78

Abstract: A ferroelectric device, for instance, a metal-ferroelectric-metal (MFM) capacitor, a ferroelectric random access memory (Fe-RAM), or a ferroelectric field effect transistor (FeFET), is provided. In one aspect, the ferroelectric device is based on hafnium zirconate (HZO). The ferroelectric device can include a first electrode and a second electrode, and a doped HZO layer, which is arranged between the first electrode and the second electrode. The doped HZO layer can include a ferroelectric layer and at least two non-zero remnant polarization charge states. The doped HZO layer can be doped with at least two different elements selected from the lanthanide series, or with a combination of at least one element selected from the lanthanide series and at least one rare earth element.

公开(公告)号：US11195767B2

公开(公告)日：2021-12-07

申请号：US16550085

申请日：2019-08-23

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Liesbeth Witters ,  Niamh Waldron ,  Robert Langer ,  Bernardette Kunert

IPC: H01L21/8258 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3065 ,  H01L29/423 ,  H01L21/308

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

公开(公告)号：US20190096764A1

公开(公告)日：2019-03-28

申请号：US16203605

申请日：2018-11-28

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert

IPC: H01L21/822 ,  H01L23/535 ,  H01L21/84 ,  H01L27/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

公开(公告)号：US20240206186A1

公开(公告)日：2024-06-20

申请号：US18540543

申请日：2023-12-14

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Jan Van Houdt

IPC: H10B51/30 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/30 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/10

Abstract: The disclosed technology relates to a ferroelectric field-effect transistor (FeFET) memory structure. The FeFET memory structure can include a substrate, including an insulator layer; a gate metal layer on the insulator layer; at least one ferroelectric material layer on the gate metal layer; and a layer structure comprising at least one wide bandgap semiconductor layer on the ferroelectric material layer, wherein the layer structure can include: a first section having a first height, and at least one second section having a second height that is smaller than the first height. The FeFET memory structure can further include a drain metal structure which is arranged on the first section of the layer structure, and one or more source metal structures, wherein each source metal structure is arranged on a respective second section of the layer structure.

公开(公告)号：US11968841B2

公开(公告)日：2024-04-23

申请号：US17650154

申请日：2022-02-07

Applicant: IMEC vzw

Inventor： Mihaela Ioana Popovici ,  Amey Mahadev Walke ,  Jan Van Houdt

IPC: H10B53/30 ,  H01L29/78 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/40 ,  H01L29/78391

Abstract: A ferroelectric device, for instance, a metal-ferroelectric-metal (MFM) capacitor, a ferroelectric random access memory (Fe-RAM), or a ferroelectric field effect transistor (FeFET), is provided. In one aspect, the ferroelectric device is based on hafnium zirconate (HZO). The ferroelectric device can include a first electrode and a second electrode, and a doped HZO layer, which is arranged between the first electrode and the second electrode. The doped HZO layer can include a ferroelectric layer and at least two non-zero remnant polarization charge states. The doped HZO layer can be doped with at least two different elements selected from the lanthanide series, or with a combination of at least one element selected from the lanthanide series and at least one rare earth element.