Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
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Application No.: US16666388Application Date: 2019-10-28
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Publication No.: US11195817B2Publication Date: 2021-12-07
- Inventor: Shih-Ya Huang , Chung-Hao Tsai , Chen-Hua Yu , Chuei-Tang Wang , Chih-Yuan Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/538 ; H01L23/31 ; H01L25/00 ; H01L23/40

Abstract:
A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat sink is fastened to the reconstructed wafer.
Public/Granted literature
- US20210125960A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-04-29
Information query
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