公开(公告)号：US20210225804A1

公开(公告)日：2021-07-22

申请号：US16745345

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: A passive device module includes a first tier, a second tier and connective terminals. The first tier includes a first semiconductor chip and a first encapsulant. The first semiconductor chip has contact posts. The encapsulant encapsulates the first semiconductor chip. The second tier is disposed on the first tier, and includes a second semiconductor chip, through interlayer walls, and a second encapsulant. The through interlayer walls are locate beside and face sidewalls of the second semiconductor chip and are electrically connected to the contact posts. The second encapsulant encapsulates the second semiconductor chip and the through interlayer walls. The connective terminals are disposed over the second tier and are electrically connected to the first semiconductor chip via the through interlayer walls. The first and second semiconductor chips include passive devices.

公开(公告)号：US20210057346A1

公开(公告)日：2021-02-25

申请号：US16547567

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Wei-Ting Chen ,  Chien-Hsun Chen ,  Shih-Ya Huang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.

公开(公告)号：US10811404B2

公开(公告)日：2020-10-20

申请号：US16218492

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L27/01 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00

Abstract: Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a passive device, and a package. The die has a front side and a backside opposite to each other. The package is disposed on the backside of the die. The passive device is disposed between the backside of the die and the package.

公开(公告)号：US11302649B2

公开(公告)日：2022-04-12

申请号：US16908284

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu ,  Chih-Yuan Chang

IPC: H01L23/552 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L23/50 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

公开(公告)号：US11211360B2

公开(公告)日：2021-12-28

申请号：US16745345

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

Abstract: A passive device module includes a first tier, a second tier and connective terminals. The first tier includes a first semiconductor chip and a first encapsulant. The first semiconductor chip has contact posts. The encapsulant encapsulates the first semiconductor chip. The second tier is disposed on the first tier, and includes a second semiconductor chip, through interlayer walls, and a second encapsulant. The through interlayer walls are locate beside and face sidewalls of the second semiconductor chip and are electrically connected to the contact posts. The second encapsulant encapsulates the second semiconductor chip and the through interlayer walls. The connective terminals are disposed over the second tier and are electrically connected to the first semiconductor chip via the through interlayer walls. The first and second semiconductor chips include passive devices.

公开(公告)号：US11195817B2

公开(公告)日：2021-12-07

申请号：US16666388

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Chih-Yuan Chang

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L23/40

Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat sink is fastened to the reconstructed wafer.

公开(公告)号：US11062998B2

公开(公告)日：2021-07-13

申请号：US16547567

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Wei-Ting Chen ,  Chien-Hsun Chen ,  Shih-Ya Huang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.

公开(公告)号：US20210125960A1

公开(公告)日：2021-04-29

申请号：US16666388

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Chih-Yuan Chang

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/40 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat sink is fastened to the reconstructed wafer.

公开(公告)号：US20200321288A1

公开(公告)日：2020-10-08

申请号：US16908284

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu ,  Chih-Yuan Chang

IPC: H01L23/552 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L23/50 ,  H01L21/683

Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

公开(公告)号：US20190371781A1

公开(公告)日：2019-12-05

申请号：US16218492

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L27/01 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a passive device, and a package. The die has a front side and a backside opposite to each other. The package is disposed on the backside of the die. The passive device is disposed between the backside of the die and the package.