In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.