公开(公告)号：US12063773B2

公开(公告)日：2024-08-13

申请号：US17589580

申请日：2022-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: G11C17/00 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/528 ,  H10B20/20

CPC classification number: H10B20/20 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5226 ,  H01L23/528

Abstract: A semiconductor device includes first and second active areas, a first gate, a first conductive segment, a first via and a first continuous gate. The first and second active areas extend in a first direction. The first gate crosses over the first active area and the second active area. The first gate includes a first gate portion and a second gate portion electrically isolated from each other. The first conductive segment crosses over the first active area and the second active area. The first via is arranged above the first conductive segment. The first active area and the second active area are coupled through the first conductive segment to the first via. The first continuous gate is disposed between the first conductive segment and the first gate, and crossing over the first active area and the second active area.

公开(公告)号：US11949799B2

公开(公告)日：2024-04-02

申请号：US17222806

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Shih-Lien Linus Lu ,  Cheng Hung Lee ,  Chia-En Huang

IPC: H04L9/32 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/08

CPC classification number: H04L9/3278 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/0861

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

公开(公告)号：US11734142B2

公开(公告)日：2023-08-22

申请号：US17651595

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung Chang ,  Atul Katoch ,  Chia-En Huang ,  Ching-Wei Wu ,  Donald G. Mikan, Jr. ,  Hao-I Yang ,  Kao-Cheng Lin ,  Ming-Chien Tsai ,  Saman M. I. Adham ,  Tsung-Yung Chang ,  Uppu Sharath Chandra

IPC: G06F11/263 ,  G06F1/10 ,  G06F11/22 ,  G06F11/267 ,  G11C29/12 ,  G11C29/32 ,  G11C29/48

CPC classification number: G06F11/263 ,  G06F1/10 ,  G06F11/2273 ,  G06F11/267 ,  G11C29/1201 ,  G11C29/32 ,  G11C29/48

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US11315936B2

公开(公告)日：2022-04-26

申请号：US16805868

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Hsun Chiu ,  Yih Wang

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/112 ,  H01L23/525

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a transistor, a first embedded insulating structure and a second embedded insulating structure. The transistor is formed on a substrate, and includes a gate structure, channel structures, a source electrode and a drain electrode. The channel structures penetrate through the gate structure, and are in contact with the source and drain electrodes. The first and second embedded insulating structures are disposed in the substrate, and overlapped with the source and drain electrodes. The first and second embedded insulating structures are laterally spaced apart from each other by a portion of the substrate lying under the gate structure.

公开(公告)号：US20210202503A1

公开(公告)日：2021-07-01

申请号：US16729973

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Wan-Hsueh Cheng ,  Yao-Jen Yang ,  Yih Wang

IPC: H01L27/112 ,  H01L23/528 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  G06F30/392

Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

公开(公告)号：US20240312995A1

公开(公告)日：2024-09-19

申请号：US18672936

申请日：2024-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Chia-En Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L21/823878 ,  H01L23/5286 ,  H01L29/0665 ,  H01L29/42392

Abstract: A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.

公开(公告)号：US20240290865A1

公开(公告)日：2024-08-29

申请号：US18498697

申请日：2023-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  I-Hsin Yang

IPC: H01L29/66 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L27/0688 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: An embodiment includes a method including forming a first conductive feature and a second conductive feature in a substrate. The method also includes forming a first complementary field-effect transistor (CFET) over the substrate, the forming including forming a first lower transistor including a first gate and a first source/drain region. The method also includes forming a first upper transistor including a second gate and a second source/drain region, the first upper transistor overlapping the first lower transistor. The method also includes forming a conductive via fuse connected to the first conductive feature and the second source/drain region.

公开(公告)号：US11955201B2

公开(公告)日：2024-04-09

申请号：US17873692

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

CPC classification number: G11C7/1051 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

公开(公告)号：US11948972B2

公开(公告)日：2024-04-02

申请号：US16916951

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Chia-En Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Yih Wang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B20/20

CPC classification number: H01L29/0673 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H10B20/20

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

公开(公告)号：US11348929B2

公开(公告)日：2022-05-31

申请号：US17035298

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Chia-En Huang ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11521 ,  H01L23/522 ,  H01L27/11568 ,  G11C7/18 ,  H01L29/872 ,  G11C8/14

Abstract: A memory device includes a substrate, a first gate structure and a second gate structure, first, second, third source/drain structures, gate spacers, a first via and a second via, and a semiconductor layer. The first gate structure and the second gate structure are over the substrate. The first, second, third source/drain structures are over the substrate, in which the first and second source/drain structures are on opposite sides of the first gate structure, the second and third source/drain structures are on opposite sides of the second gate structure. The gate spacers are on opposite sidewalls of the first and second gate structures. The first via and the second via are over the first gate structure and the second gate structure, respectively, in which the first via is in contact with the first gate structure. The semiconductor layer is between the second via and the second gate structure.