公开(公告)号：US11949799B2

公开(公告)日：2024-04-02

申请号：US17222806

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Shih-Lien Linus Lu ,  Cheng Hung Lee ,  Chia-En Huang

IPC: H04L9/32 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/08

CPC classification number: H04L9/3278 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/0861

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

公开(公告)号：US10978144B2

公开(公告)日：2021-04-13

申请号：US16572625

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-En Huang ,  Hidehiro Fujiwara ,  Jui-Che Tsai ,  Yen-Huei Chen ,  Yih Wang

IPC: G11C7/00 ,  G11C11/419 ,  H01L27/11 ,  G11C5/06 ,  G11C11/418

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

公开(公告)号：US10511309B1

公开(公告)日：2019-12-17

申请号：US16230088

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus Lu ,  Cheng-En Lee ,  Jui-Che Tsai

IPC: H03K19/177 ,  G06F12/14 ,  G11C16/22 ,  H04L9/32 ,  G06F21/72

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.

公开(公告)号：US10972292B2

公开(公告)日：2021-04-06

申请号：US16383383

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Shih-Lien Linus Lu ,  Cheng Hung Lee ,  Chia-En Huang

IPC: H04L9/32 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/08

Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

公开(公告)号：US20210098035A1

公开(公告)日：2021-04-01

申请号：US16876138

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Chia-En Huang ,  Yu-Hao Hsu ,  Yih Wang

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

Abstract: In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

公开(公告)号：US11200924B2

公开(公告)日：2021-12-14

申请号：US16876138

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Chia-En Huang ,  Yu-Hao Hsu ,  Yih Wang

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06

Abstract: In an exemplary embodiment, the disclosure provides a memory circuit which includes a dual port memory cell for storing a binary value accessed through a first port and a second port, a first WL switch connected to the dual port memory cell and controlled by a first WL voltage, a second WL switch connected to the dual port memory cell and controlled by a second WL voltage, a BL connected to the first WL switch for accessing the memory cell through the first port and having a first BL voltage, a second BL connected to the second WL switch for accessing the memory cell through the second port and having a second BL voltage, a BL selection circuit connected to the second WL switch for selecting the second BL, and a BL voltage pull down circuit connected to the BL selection circuit and the second WL switch.

公开(公告)号：US10164640B1

公开(公告)日：2018-12-25

申请号：US16004209

申请日：2018-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus Lu ,  Cheng-En Lee ,  Jui-Che Tsai

IPC: H03K19/003 ,  H03K19/177 ,  G06F21/72 ,  H04L9/32 ,  G11C16/22 ,  G06F12/14

Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.

公开(公告)号：US20210082495A1

公开(公告)日：2021-03-18

申请号：US16572625

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-En Huang ,  Hidehiro Fujiwara ,  Jui-Che Tsai ,  Yen-Huei Chen ,  Yih Wang

IPC: G11C11/419 ,  G11C11/418 ,  G11C5/06 ,  H01L27/11

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

公开(公告)号：US10666438B2

公开(公告)日：2020-05-26

申请号：US16160397

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Che Tsai ,  Cheng Hung Lee ,  Shih-Lien Linus Lu ,  Yi-Ju Chen

IPC: H04L9/32 ,  G11C7/08 ,  G11C7/12 ,  G06F21/73

Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates. This physical uniqueness of the bitlines can be utilized to implement a physical unclonable function (PUF) allowing the memory storage device to be differentiated from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process.