- 专利标题: Memory devices and electronic systems having a hybrid cache including static and dynamic caches that may be selectively disabled based on cache workload or availability, and related methods
-
申请号: US16396432申请日: 2019-04-26
-
公开(公告)号: US11204696B2公开(公告)日: 2021-12-21
- 发明人: Kishore K. Muchherla , Ashutosh Malshe , Sampath K. Ratnam , Peter Feeley , Michael G. Miller , Christopher S. Hale , Renato C. Padilla
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: TraskBritt
- 主分类号: G06F3/06
- IPC分类号: G06F3/06 ; G06F12/02 ; G06F12/0888 ; G06F11/34 ; G06F12/0893
摘要:
Memory devices including a hybrid cache, methods of operating a memory device, and associated electronic systems including a memory device having a hybrid cache, are disclosed. The hybrid cache includes a dynamic cache that may include x-level cell (XLC) blocks of non-volatile memory cells, which may include multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), etc., shared between the dynamic cache and a main memory. The hybrid cache includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache based on a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. The cache may be disabled based on, for example, program/erase (PE) cycles of one or more portions of the memory device or the workload exceeding a threshold, which may define one or more switch points. A method of operating a memory device may include writing data in the static cache if the static cache is available, and writing the data in the dynamic cache if the static cache is unavailable.