Invention Grant
- Patent Title: Power backup architecture using capacitor
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Application No.: US16525231Application Date: 2019-07-29
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Publication No.: US11218019B2Publication Date: 2022-01-04
- Inventor: Vehid Suljic , Matthew D. Rowley
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H02J7/00
- IPC: H02J7/00 ; G01R31/392 ; G01R31/36 ; G01R31/396 ; H01M10/46 ; H01M10/48 ; H01M10/52 ; G01R31/14 ; G01R27/28 ; G06F13/28 ; H02J7/34 ; H02J9/06 ; G06F3/06

Abstract:
Various embodiments described herein use a set of capacitor sets (e.g., capacitor banks) in a power backup architecture for a memory sub-system, where each capacitor set can be individually checked for a health condition (e.g., in parallel) to determine their respective health after the memory sub-system has completed a boot process. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the memory sub-system can perform certain operations prior to primary power loss to the memory sub-system (e.g., preemptively performs a data backup process to ensure data integrity) and can adjust the operational mode of the memory sub-system (e.g., switch it from read-write mode to read-only mode).
Public/Granted literature
- US20210036540A1 POWER BACKUP ARCHITECTURE USING CAPACITOR Public/Granted day:2021-02-04
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