公开(公告)号：US20220415368A1

公开(公告)日：2022-12-29

申请号：US17897929

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G11C5/14 ,  G06F1/3296 ,  G06F1/28

Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.

公开(公告)号：US11430489B2

公开(公告)日：2022-08-30

申请号：US17016544

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/00 ,  G11C5/14 ,  G06F1/3296 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3215

Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.

公开(公告)号：US20220085645A1

公开(公告)日：2022-03-17

申请号：US17534168

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Vehid Suljic ,  Matthew D. Rowley

IPC: H02J7/34 ,  H02J9/06 ,  H02J7/00 ,  G06F3/06

Abstract: Various embodiments described herein use a set of capacitor sets (e.g., capacitor banks) in a power backup architecture for a memory sub-system, where each capacitor set can be individually checked for a health condition (e.g., in parallel) to determine their respective health after the memory sub-system has completed a boot process. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the memory sub-system can perform certain operations prior to primary power loss to the memory sub-system (e.g., preemptively performs a data backup process to ensure data. integrity) and can adjust the operational mode of the memory sub-system (e.g., switch it from read-write mode to read-only mode).

公开(公告)号：US11269397B2

公开(公告)日：2022-03-08

申请号：US16996256

申请日：2020-08-18

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Adam J. Hieb

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F9/445 ,  G06F1/3296

Abstract: A power management system includes a memory component storing a plurality of configuration profiles. A plurality of configuration pins are operatively coupled to the memory component. One or more of the plurality of configuration pins receive one or more signals to selectively activate one of the plurality of configuration profiles.

公开(公告)号：US11409348B2

公开(公告)日：2022-08-09

申请号：US16524933

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Vehid Suljic ,  Matthew D. Rowley

IPC: G06F1/28 ,  G11C5/14 ,  G06F1/30 ,  G06F3/06 ,  H02J7/34

Abstract: Various embodiments described herein use a plurality of capacitor sets (e.g., capacitor banks) in a power backup architecture for an electronic system (e.g., memory sub-system), where each capacitor set can be individually checked against a health condition (e.g., in parallel) to determine their respective health during power-up of an electronic system or during normal operation of the electronic system. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the electronic system can perform certain operations prior to primary power loss to the electronic system (e.g., memory sub-system preemptively performs a data backup process to data integrity) and can adjust the operational mode of the electronic system (e.g., memory sub-system switches from read-write mode to read-only mode).

公开(公告)号：US11226671B2

公开(公告)日：2022-01-18

申请号：US16287162

申请日：2019-02-27

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley

IPC: G06F1/3234 ,  G11C16/30 ,  G06F1/26

Abstract: An apparatus includes a power management integrated circuit (PMIC) and a power translator component coupled to the PMIC. The power translator component supplies power to the PMIC. The power translator component can further receive, from the PMIC, an indication that the PMIC has experienced a thermal event and responsive to receipt of the indication that the PMIC has experienced the thermal event, prevent powering of the PMIC.

公开(公告)号：US11218019B2

公开(公告)日：2022-01-04

申请号：US16525231

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Vehid Suljic ,  Matthew D. Rowley

IPC: H02J7/00 ,  G01R31/392 ,  G01R31/36 ,  G01R31/396 ,  H01M10/46 ,  H01M10/48 ,  H01M10/52 ,  G01R31/14 ,  G01R27/28 ,  G06F13/28 ,  H02J7/34 ,  H02J9/06 ,  G06F3/06

Abstract: Various embodiments described herein use a set of capacitor sets (e.g., capacitor banks) in a power backup architecture for a memory sub-system, where each capacitor set can be individually checked for a health condition (e.g., in parallel) to determine their respective health after the memory sub-system has completed a boot process. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the memory sub-system can perform certain operations prior to primary power loss to the memory sub-system (e.g., preemptively performs a data backup process to ensure data integrity) and can adjust the operational mode of the memory sub-system (e.g., switch it from read-write mode to read-only mode).

公开(公告)号：US20210036540A1

公开(公告)日：2021-02-04

申请号：US16525231

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Vehid Suljic ,  Matthew D. Rowley

IPC: H02J7/34 ,  G06F3/06 ,  H02J7/00 ,  H02J9/06

Abstract: Various embodiments described herein use a set of capacitor sets (e.g., capacitor banks) in a power backup architecture for a memory sub-system, where each capacitor set can be individually checked for a health condition (e.g., in parallel) to determine their respective health after the memory sub-system has completed a boot process. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the memory sub-system can perform certain operations prior to primary power loss to the memory sub-system (e.g., preemptively performs a data backup process to ensure data integrity) and can adjust the operational mode of the memory sub-system (e.g., switch it from read-write mode to read-only mode).

公开(公告)号：US20210021689A1

公开(公告)日：2021-01-21

申请号：US17064542

申请日：2020-10-06

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Mark Bauer

IPC: H04L29/08 ,  H04W88/06 ,  H04L29/06 ,  H04W88/16 ,  G06F13/16

Abstract: A memory device includes a communication circuit configured to communicate a first signal and a second signal; and a selection mechanism coupled to the communication circuit and configured to select between operating the communication circuit the first signal and the second signal (1) independent signals for separate memory operations or (2) a complementary set for a memory operation.

公开(公告)号：US10861567B2

公开(公告)日：2020-12-08

申请号：US16684924

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Matthew D. Rowley ,  Dustin J. Carter

IPC: G11C5/14 ,  G11C16/30 ,  G06F1/26 ,  G05F1/46 ,  G06F1/28 ,  G01R19/165 ,  G11C16/10 ,  H02M3/158

Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.