Invention Grant
- Patent Title: In-memory computation device
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Application No.: US17006493Application Date: 2020-08-28
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Publication No.: US11221827B1Publication Date: 2022-01-11
- Inventor: Po-Kai Hsu , Teng-Hao Yeh , Tzu-Hsuan Hsu , Hang-Ting Lue
- Applicant: MACRONIX International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX International Co., Ltd.
- Current Assignee: MACRONIX International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: J.C. Patents
- Main IPC: G06F7/544
- IPC: G06F7/544 ; G06G7/16 ; G06G7/14 ; G06F7/501

Abstract:
An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.
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