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公开(公告)号：US20240170076A1
公开(公告)日：2024-05-23
申请号：US17988773
申请日：2022-11-17
发明人： Teng-Hao Yeh , Hang-Ting Lue , Tzu-Hsuan Hsu , Chen-Huan Chen , Ken-Hui Chen
CPC分类号： G11C16/3459 , G11C7/1039 , G11C16/08 , G11C16/24
摘要： A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.
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公开(公告)号：US11875854B2
公开(公告)日：2024-01-16
申请号：US17710683
申请日：2022-03-31
发明人： Teng Hao Yeh , Wu-Chin Peng , Chih-Ming Lin , Hang-Ting Lue
摘要： A memory device and a word line driver thereof are provided. The word line driver includes a first word line signal generator, a second word line signal generator, a first voltage generator, and a second voltage generator. The first word line signal generator selects one of a first voltage and a second voltage to generate a first word line signal according a control signal. The second word line signal generator selects one of a third voltage and a fourth voltage to generate a second word line signal according the control signal. The first voltage generator provides the second voltage, and the second voltage generator provides the fourth voltage, where the first voltage generator is independent to the second voltage generator.
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公开(公告)号：US20230413552A1
公开(公告)日：2023-12-21
申请号：US17845601
申请日：2022-06-21
发明人： Hang-Ting Lue , Teng Hao Yeh , Cheng-Yu Lee , Wei-Chen Chen
IPC分类号： H01L27/11582 , H01L23/535 , H01L27/11573
CPC分类号： H01L27/11582 , H01L27/11573 , H01L23/535
摘要： A three-dimensional flash memory device may be a AND flash memory device. The three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of conductive pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.
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公开(公告)号：US20230082361A1
公开(公告)日：2023-03-16
申请号：US17475932
申请日：2021-09-15
发明人： Chih-Wei Hu , Teng-Hao Yeh , Hang-Ting Lue
IPC分类号： H01L27/11582 , H01L27/11556
摘要： A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.
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公开(公告)号：US20220013535A1
公开(公告)日：2022-01-13
申请号：US16924001
申请日：2020-07-08
发明人： Hang-Ting Lue
IPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/11519 , H01L27/1157 , H01L27/11565 , H01L29/417
摘要： Provided are various three-dimensional flash memory devices. A three-dimensional flash memory device includes a gate stacked structure, separate arc-shaped channel pillars, source/drain pillars and a charge storage structure. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The arc-shaped channel pillar are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate and penetrate through the gate stacked structure, wherein two source/drain pillars are disposed at two ends of each of the arc-shaped channel pillars. The charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel pillar.
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公开(公告)号：US11221827B1
公开(公告)日：2022-01-11
申请号：US17006493
申请日：2020-08-28
发明人： Po-Kai Hsu , Teng-Hao Yeh , Tzu-Hsuan Hsu , Hang-Ting Lue
摘要： An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.
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公开(公告)号：US20210125671A1
公开(公告)日：2021-04-29
申请号：US16667536
申请日：2019-10-29
发明人： Hang-Ting Lue
摘要： An integrated circuit and a computing method thereof are provided. The integrated circuit includes a memory array, word lines, bit lines and a page buffer. The memory array includes memory cells, each configured to be programmed with a weight. The word lines respectively connect a row of the memory cells. The bit lines are respectively connected with a column of the memory cells that are connected in series. More than one of the bit lines in a block of the memory array or more than one of the word lines in multiple blocks of the memory array are configured to receive input voltages. The memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages. The page buffer is coupled to the memory array, and configured to sense products of the weights and the input voltages.
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公开(公告)号：US20200098774A1
公开(公告)日：2020-03-26
申请号：US16142901
申请日：2018-09-26
发明人： Teng-Hao Yeh , Hang-Ting Lue
IPC分类号： H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.
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公开(公告)号：US10566348B1
公开(公告)日：2020-02-18
申请号：US16180970
申请日：2018-11-05
发明人： Teng-Hao Yeh , Hang-Ting Lue
IPC分类号： H01L29/792 , H01L27/11582 , H01L29/10 , H01L23/528 , H01L21/8234
摘要： A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.
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公开(公告)号：US10535673B2
公开(公告)日：2020-01-14
申请号：US15996617
申请日：2018-06-04
发明人： Teng-Hao Yeh , Chih-Wei Hu , Hang-Ting Lue
IPC分类号： H01L27/11 , H01L27/11556 , G11C16/10 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L27/11565 , G11C16/04 , G11C11/56 , H01L27/11519
摘要： A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.
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