Invention Grant
- Patent Title: Cut metal gate process for reducing transistor spacing
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Application No.: US16854627Application Date: 2020-04-21
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Publication No.: US11239072B2Publication Date: 2022-02-01
- Inventor: Ming-Chang Wen , Chang-Yun Chang , Hsien-Chin Lin , Hung-Kai Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/3215 ; H01L21/3105 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L21/8258 ; H01L21/8238 ; H01L21/762 ; H01L27/11 ; H01L27/02

Abstract:
A semiconductor structure includes a substrate, a pair of first fins extending from the substrate, a pair of second fins extending from the substrate, an isolation feature over the substrate and separating bottom portions of the first and the second fins, a pair of first epitaxial semiconductor features over the pair of first fins respectively, a pair of second epitaxial semiconductor features over the pair of second fins respectively, and a first dielectric feature sandwiched between and separating the pair of first epitaxial semiconductor features. The pair of second epitaxial semiconductor features merge with each other.
Public/Granted literature
- US20200251325A1 Cut Metal Gate Process for Reducing Transistor Spacing Public/Granted day:2020-08-06
Information query
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