Invention Grant
- Patent Title: Technologies for efficient stochastic associative search operations with error-correcting code
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Application No.: US16367320Application Date: 2019-03-28
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Publication No.: US11262913B2Publication Date: 2022-03-01
- Inventor: Jawad B. Khan , Richard Coulson
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F11/10 ; G11C29/52 ; G11C29/04

Abstract:
Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) using error correction codes include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The compute device identifies, based on a search performed on the columns in the matrix, one or more candidate data sets. Each candidate data set corresponds to one of the rows in the matrix. The compute device performs an error correction operation on the identified one or more candidate data sets to determine whether the identified one or more candidate data sets is an exact match with the subset of the bit data.
Public/Granted literature
- US20190220202A1 TECHNOLOGIES FOR EFFICIENT STOCHASTIC ASSOCIATIVE SEARCH OPERATIONS WITH ERROR-CORRECTING CODE Public/Granted day:2019-07-18
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