A semiconductor memory device includes separate first and second word lines respectively facing first and second portions of a semiconductor and sandwiching the semiconductor; and first and second cell transistors respectively located in the first and second portions and respectively coupled to the first and second word lines. In a first operation, a first read is executed on the second cell transistor while a first voltage and a higher second voltage are being respectively applied to the first and second word lines. In a second operation, a second read is executed on the first cell transistor while a third voltage between the first and second voltages is being applied to the second word line.