-
公开(公告)号：US11923012B2
公开(公告)日：2024-03-05
申请号：US17962302
申请日：2022-10-07
申请人： KIOXIA CORPORATION
发明人： Hiroshi Maejima
CPC分类号： G11C16/10 , G06F3/0614 , G06F3/0631 , G06F3/0652 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0246 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3418 , G06F2212/1032 , G06F2212/152 , G06F2212/214 , G06F2212/7202 , G11C2213/71
摘要： A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
-
公开(公告)号：US11715533B2
公开(公告)日：2023-08-01
申请号：US17377857
申请日：2021-07-16
申请人： KIOXIA CORPORATION
发明人： Hiroshi Maejima
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3418 , G11C16/3459
摘要： A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
-
公开(公告)号：US11594546B2
公开(公告)日：2023-02-28
申请号：US16795763
申请日：2020-02-20
申请人： KIOXIA CORPORATION
发明人： Naohito Morozumi , Hiroshi Maejima
IPC分类号： H01L27/1157 , G11C16/16 , H01L27/11573 , H01L27/11565 , G11C16/26 , G11C16/08 , G11C16/24 , H01L23/00 , G11C7/06
摘要： A semiconductor memory device according to an embodiment includes a memory chip and a circuit chip. The memory chip includes first and second joint metals. The circuit chip includes first and second sense amplifiers, and third and fourth joint metals facing the first and second joint metals, respectively. The first sense amplifier includes first and second active regions. The first active region includes a first transistor coupled between the third joint metal and the second active region. The second amplifier includes third and fourth active region. The third active region includes a second transistor coupled between the fourth joint metal and the fourth active region. The third and fourth joint metals overlap the first and third active regions, respectively.
-
4.发明授权公开(公告)号：US11538791B2
公开(公告)日：2022-12-27
申请号：US16802462
申请日：2020-02-26
申请人： KIOXIA CORPORATION
IPC分类号： H01L25/065 , H01L25/18 , H01L23/00
摘要： A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.
-
公开(公告)号：US11282568B2
公开(公告)日：2022-03-22
申请号：US17008452
申请日：2020-08-31
申请人： KIOXIA CORPORATION
发明人： Hiroshi Maejima
IPC分类号： G11C11/4094 , G11C7/10 , G11C5/06 , G11C11/4097 , G11C11/408 , G11C11/4074 , G11C11/4091
摘要： A semiconductor storage device includes a memory unit and a circuit unit bonded to the memory unit. The memory unit includes first and second memory cells, first and second bit lines respectively connected to the first and second memory cells, and first and second bonding metals respectively connected to the first and second bit lines. The circuit unit includes a sense amplifier unit including a first wire, a third bonding metal connected with the first wire and opposed to the first bonding metal, and a fourth bonding metal connected with the first wire and opposed to the second bonding metal.
-
公开(公告)号：US11990190B2
公开(公告)日：2024-05-21
申请号：US18332472
申请日：2023-06-09
申请人： Kioxia Corporation
发明人： Hiroshi Maejima
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3418 , G11C16/3459
摘要： A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
-
公开(公告)号：US11967380B2
公开(公告)日：2024-04-23
申请号：US17841362
申请日：2022-06-15
申请人： Kioxia Corporation
发明人： Hiroshi Maejima
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/16
摘要： According to One embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.
-
公开(公告)号：US11929352B2
公开(公告)日：2024-03-12
申请号：US17984959
申请日：2022-11-10
申请人： KIOXIA CORPORATION
IPC分类号： H01L25/065 , H01L23/00 , H01L25/18
CPC分类号： H01L25/0657 , H01L24/08 , H01L25/18 , H01L2224/08145 , H01L2225/06524 , H01L2924/1431 , H01L2924/14511
摘要： A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.
-
公开(公告)号：US11894070B2
公开(公告)日：2024-02-06
申请号：US18156654
申请日：2023-01-19
申请人： KIOXIA CORPORATION
发明人： Takeshi Hioka , Tsukasa Kobayashi , Koji Kato , Yuki Shimizu , Hiroshi Maejima
摘要： According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.
-
公开(公告)号：US11508697B2
公开(公告)日：2022-11-22
申请号：US16806079
申请日：2020-03-02
申请人： Kioxia Corporation
发明人： Tomoya Sanuki , Hiroshi Maejima , Tetsuaki Utsumi
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18
摘要： According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.
-
-
-
-
-
-
-
-
-
搜索结果
34 条记录 (耗时 0.018 秒)
