Invention Grant
- Patent Title: Via resistance reduction
-
Application No.: US16958654Application Date: 2018-03-16
-
Publication No.: US11271042B2Publication Date: 2022-03-08
- Inventor: Anna Maria Conti , Cristina Casellato , Andrea Redaelli
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- International Application: PCT/US2018/023019 WO 20180316
- International Announcement: WO2019/177632 WO 20190919
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L21/768 ; H01L23/522

Abstract:
One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact.
Public/Granted literature
- US20210066394A1 VIA RESISTANCE REDUCTION Public/Granted day:2021-03-04
Information query
IPC分类: