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    Via resistance reduction
    1.
    发明授权
    Via resistance reduction 有权

    公开(公告)号：US11271042B2

    公开(公告)日：2022-03-08

    申请号：US16958654

    申请日：2018-03-16

    Applicant: INTEL CORPORATION

    Inventor： Anna Maria Conti ,  Cristina Casellato ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L21/768 ,  H01L23/522

    Abstract: One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact.

    Memory structures having reduced via resistance
    4.
    发明授权
    Memory structures having reduced via resistance 有权

    公开(公告)号：US10600844B2

    公开(公告)日：2020-03-24

    申请号：US16147264

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Anna Maria Conti ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A memory structure can include a memory cell, a via, a dielectric material separating the memory cell from the via, a metal ceramic composite material layer on the memory cell and the dielectric material, and a conductive layer on the metal ceramic composite material layer and the via. The conductive layer can be in direct contact with the top surface of the via.

    Memory device with double protective liner
    5.
    发明授权
    Memory device with double protective liner 有权

    公开(公告)号：US11647638B2

    公开(公告)日：2023-05-09

    申请号：US16295687

    申请日：2019-03-07

    Applicant: INTEL CORPORATION

    Inventor： Anna Maria Conti ,  Fabio Pellizzer ,  Agostino Pirovano ,  Kolya Yastrebenetsky

    IPC: H01L23/528 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

    Abstract: A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.

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