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    Via resistance reduction
    2.
    发明授权
    Via resistance reduction 有权

    公开(公告)号：US11271042B2

    公开(公告)日：2022-03-08

    申请号：US16958654

    申请日：2018-03-16

    Applicant: INTEL CORPORATION

    Inventor： Anna Maria Conti ,  Cristina Casellato ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L21/768 ,  H01L23/522

    Abstract: One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact.

    Deck-to-deck reset current offset suppression for three-dimensional (3D) memory
    6.
    发明授权
    Deck-to-deck reset current offset suppression for three-dimensional (3D) memory 有权

    公开(公告)号：US10825863B2

    公开(公告)日：2020-11-03

    申请号：US16361030

    申请日：2019-03-21

    Applicant: Intel Corporation

    Inventor： Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: A three-dimensional (3D) memory device includes multiple decks of memory cells. Each deck includes layers of material, including a layer of storage material (e.g., a phase change material). Each deck also includes an interlayer between the phase change material and conductive access lines. The interlayer can include, for example, one or more of tungsten, carbon, silicon, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and titanium silicon nitride. In one such example, the interlayer includes tungsten silicon nitride (WSiN). The interlayers of different decks have different properties, such as different thicknesses or resistivities, to reduce or eliminate the deck-to-deck reset current offset.

    Reset refresh techniques for self-selecting memory
    7.
    发明授权
    Reset refresh techniques for self-selecting memory 有权

    公开(公告)号：US10777275B2

    公开(公告)日：2020-09-15

    申请号：US16143033

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： Agostino Pirovano ,  Hernan A. Castro ,  Innocenzo Tortorelli ,  Andrea Redaelli

    IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: Reset refresh techniques are described, which can enable reducing or canceling the drift of threshold voltage distributions exhibited by memory cells. In one example a memory device includes an array of memory cells. The memory cells include a chalcogenide storage material. The memory device includes hardware logic to program the memory cells, including logic to detect whether a memory cell is selectable with a first voltage having a first polarity. In response to detection that a memory cell is not selectable with the first voltage, the memory cell is refreshed the memory cell with a second voltage that has a polarity opposite to the first voltage. After the refresh with the second voltage, the memory cell can be programmed with the first voltage having the first polarity.

    Memory device with increased electrode resistance to reduce transient selection current
    9.
    发明授权
    Memory device with increased electrode resistance to reduce transient selection current 有权

    公开(公告)号：US11264567B2

    公开(公告)日：2022-03-01

    申请号：US16688309

    申请日：2019-11-19

    Applicant: INTEL CORPORATION

    Inventor： Srivatsan Venkatesan ,  Davide Mantegazza ,  John Gorman ,  Iniyan Soundappa Elango ,  Davide Fugazza ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Various embodiments of a three-dimensional cross-point (3D X-point) memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

    Memory structures having reduced via resistance
    10.
    发明授权
    Memory structures having reduced via resistance 有权

    公开(公告)号：US10600844B2

    公开(公告)日：2020-03-24

    申请号：US16147264

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Anna Maria Conti ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A memory structure can include a memory cell, a via, a dielectric material separating the memory cell from the via, a metal ceramic composite material layer on the memory cell and the dielectric material, and a conductive layer on the metal ceramic composite material layer and the via. The conductive layer can be in direct contact with the top surface of the via.

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