Invention Grant
- Patent Title: Photonics systems to enable top-side wafer-level optical and electrical test
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Application No.: US16856387Application Date: 2020-04-23
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Publication No.: US11280959B2Publication Date: 2022-03-22
- Inventor: Roy Edward Meade , Chen Sun , Shahab Ardalan , John Fini , Forrest Sedgwick
- Applicant: Ayar Labs, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Ayar Labs, Inc.
- Current Assignee: Ayar Labs, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Penilla IP, APC
- Main IPC: G02B6/13
- IPC: G02B6/13 ; G02B6/12 ; H01L21/66 ; G01M11/00

Abstract:
An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.
Public/Granted literature
- US20200341191A1 Photonics Systems to Enable Top-Side Wafer-Level Optical and Electrical Test Public/Granted day:2020-10-29
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